公开(公告)号：US20240055371A1

公开(公告)日：2024-02-15

申请号：US18151556

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Kuo-Chiang Ting ,  Yu-Hsiung Wang ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Cheng-Wei Huang ,  Yen-Ping Wang ,  Chang-Wen Huang ,  Sheng-Ta Lin ,  Li-Cheng Hu ,  Gao-Long Wu

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L23/481 ,  H01L23/3178 ,  H01L21/565

Abstract: Embodiments include a crack stopper structure surrounding an embedded integrated circuit die, and the formation thereof. The crack stopper structure may include multiple layers separated by a fill layer. The layers of the crack stopper may include multiple sublayers, some of the sublayers providing adhesion, hardness buffering, and material gradients for transitioning from one layer of the crack stopper structure to another layer of the crack stopper structure.

公开(公告)号：US20230350142A1

公开(公告)日：2023-11-02

申请号：US18347188

申请日：2023-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/42 ,  H01L23/00

CPC classification number: G02B6/4255 ,  H01L24/16 ,  H01L24/81 ,  G02B6/4246 ,  G02B6/4243 ,  H01L2224/81815 ,  H01L2224/16148 ,  H01L23/481

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

公开(公告)号：US20230124804A1

公开(公告)日：2023-04-20

申请号：US18068064

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20220383944A1

公开(公告)日：2022-12-01

申请号：US17883910

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Kuo-Chiang Ting ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L27/088 ,  H03K19/20

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

公开(公告)号：US20220365278A1

公开(公告)日：2022-11-17

申请号：US17873779

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/122

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

公开(公告)号：US20220262742A1

公开(公告)日：2022-08-18

申请号：US17339745

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Weiming Chris Chen ,  Kuo-Chiang Ting ,  Hsien-Pin Hu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.

公开(公告)号：US11380611B2

公开(公告)日：2022-07-05

申请号：US16919298

申请日：2020-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiming Chris Chen ,  Kuo-Chiang Ting ,  Shang-Yun Hou

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

Abstract: A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material.

公开(公告)号：US20210082894A1

公开(公告)日：2021-03-18

申请号：US16572619

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiming Chris Chen ,  Chi-Hsi Wu ,  Chih-Wei Wu ,  Kuo-Chiang Ting ,  Szu-Wei Lu ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Hsien-Ju Tsou ,  Cheng-Chieh Li

IPC: H01L25/18 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56

Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

公开(公告)号：US20250105172A1

公开(公告)日：2025-03-27

申请号：US18543799

申请日：2023-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Ming-Zhi Yang ,  Gao-Long Wu

IPC: H01L23/00 ,  H01L23/538

Abstract: An embodiment includes a method including forming a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization patterns therein. The method also includes forming a redistribution via and a redistribution pad over the first interconnect structure, the redistribution via and the redistribution pad being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution via and the redistribution pad having a same material composition. The method also includes forming a warpage control dielectric layer over the redistribution pad. The method also includes forming a bond via and a bond pad over the redistribution pad, the bond pad being in the warpage control dielectric layer, the bond via being electrically coupled to the redistribution pad.

公开(公告)号：US12259578B2

公开(公告)日：2025-03-25

申请号：US18358749

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Kuo Hsia ,  Chen-Hua Yu ,  Kuo-Chiang Ting ,  Shang-Yun Hou

IPC: G02B6/12 ,  G02B6/124 ,  G02B6/13

Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.