公开(公告)号：US20200020582A1

公开(公告)日：2020-01-16

申请号：US16058095

申请日：2018-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L21/768 ,  H01L21/311

Abstract: A structure and a formation method of a semiconductor device structure are provided. The method includes forming a first fin structure, a second fin structure, and a third fin structure over a semiconductor substrate. The method includes forming first spacer elements over sidewalls of the first fin structure and the second fin structure and partially removing the first fin structure and the second fin structure. The method includes forming second spacer elements over sidewalls of the third fin structure and partially removing the third fin structure. The second spacer element is taller than the first spacer element. The method includes epitaxially growing a semiconductor material over the first fin structure, the second fin structure, and the third fin structure such that a merged semiconductor element is formed on the first fin structure and the second fin structure, and a semiconductor element is formed on the third fin structure.

公开(公告)号：US20200020544A1

公开(公告)日：2020-01-16

申请号：US16035159

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Ming CHANG ,  Chih-Cheng LIN ,  Chi-Ying WU ,  Wei-Ming YOU ,  Ziwei FANG ,  Huang-Lin CHAO

IPC: H01L21/322 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L29/165

Abstract: A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.

公开(公告)号：US20190097051A1

公开(公告)日：2019-03-28

申请号：US15893081

申请日：2018-02-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Shahaji B. MORE ,  Cheng-Yi PENG ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Ziwei FANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/165 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/06

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure extended above a substrate and a gate structure formed over a middle portion of the fin structure. The middle portion of the fin structure is wrapped by the gate structure. The FinFET device structure includes a source/drain (S/D) structure adjacent to the gate structure, and the S/D structure includes a doped region at an outer portion of the S/D structure, and the doped region includes gallium (Ga). The FinFET device structure includes a metal silicide layer formed over the doped region of the S/D structure, and the metal silicide layer is in direct contact with the doped region of the S/D structure.

公开(公告)号：US20180308765A1

公开(公告)日：2018-10-25

申请号：US16016862

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei YU ,  Chia Ping LO ,  Liang-Gi YAO ,  Weng CHANG ,  Yee-Chia YEO ,  Ziwei FANG

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/268 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/268 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer including an amorphous material is formed over the first and second fin elements, where the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer. The amorphous material of the first layer remains amorphous during the performing of the anneal process.

公开(公告)号：US20180005869A1

公开(公告)日：2018-01-04

申请号：US15197984

申请日：2016-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei YU ,  Tsu-Hsiu PERNG ,  Ziwei FANG

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/02354 ,  H01L21/768 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.