公开(公告)号：US08916955B2

公开(公告)日：2014-12-23

申请号：US13745913

申请日：2013-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chow Peng ,  Jaw-Juinn Horng ,  Szu-Lin Liu ,  Po-Zeng Kang

IPC: H01L29/06 ,  G06F17/50 ,  H01L25/00

CPC classification number: H01L27/0207 ,  G06F17/5063 ,  G06F17/5068 ,  G06F17/5081 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a layout arrangement and method to minimize the area overhead associated with a transition between a semiconductor device array and background features. A nearly buffer zone free layout methodology is proposed, wherein an array of square unit cells with a first pattern density value is surrounded by background features with a second pattern density value. A difference between the first pattern density value and second pattern density value results in a density gradient at an edge of the array. Unit cells on the edge of the array which are impacted by a shape tolerance stress resulting from the density gradient are identified and reconfigured from a square shape aspect ratio to a rectangular shape aspect ratio with along axis of the unit cell oriented in a direction parallel to the variation induced shape tolerance stress to alleviate the variation.

Abstract translation: 本发明涉及一种使与半导体器件阵列与背景特征之间的转变相关联的面积开销最小化的布局布置和方法。 提出了几乎无缓冲区的布局方法，其中具有第一图案密度值的正方形单元阵列被具有第二图案密度值的背景特征所包围。 第一图案密度值和第二图案密度值之间的差异导致阵列边缘处的密度梯度。 由阵列的边缘产生的由密度梯度产生的形状公差应力影响的单位单元被识别并从正方形长宽比重新配置成矩形形状长宽比，沿着平行于 变异引起的形状公差应力减轻变异。

公开(公告)号：US20140103494A1

公开(公告)日：2014-04-17

申请号：US13745913

申请日：2013-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Chow Peng ,  Jaw-Juinn Horng ,  Szu-Lin Liu ,  Po-Zeng Kang

IPC: G06F17/50 ,  H01L25/00

CPC classification number: H01L27/0207 ,  G06F17/5063 ,  G06F17/5068 ,  G06F17/5081 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a layout arrangement and method to minimize the area overhead associated with a transition between a semiconductor device array and background features. A nearly buffer zone free layout methodology is proposed, wherein an array of square unit cells with a first pattern density value is surrounded by background features with a second pattern density value. A difference between the first pattern density value and second pattern density value results in a density gradient at an edge of the array. Unit cells on the edge of the array which are impacted by a shape tolerance stress resulting from the density gradient are identified and reconfigured from a square shape aspect ratio to a rectangular shape aspect ratio with along axis of the unit cell oriented in a direction parallel to the variation induced shape tolerance stress to alleviate the variation.

Abstract translation: 本发明涉及一种使与半导体器件阵列与背景特征之间的转变相关联的面积开销最小化的布局布置和方法。 提出了几乎无缓冲区的布局方法，其中具有第一图案密度值的正方形单元阵列被具有第二图案密度值的背景特征所包围。 第一图案密度值和第二图案密度值之间的差异导致阵列边缘处的密度梯度。 由阵列的边缘产生的由密度梯度产生的形状公差应力影响的单位单元被识别并从正方形长宽比重新配置成矩形形状长宽比，沿着平行于 变异引起的形状公差应力减轻变异。

公开(公告)号：US20130285190A1

公开(公告)日：2013-10-31

申请号：US13744532

申请日：2013-01-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Chow Peng ,  Wen-Shen Chou ,  Jui-Cheng Huang

IPC: G06F17/50 ,  H01L27/04

CPC classification number: G06F17/5072 ,  H01L27/0207 ,  H01L27/04

Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.

Abstract translation: 公开了一种多步密度梯度平滑布局样式，其中多个单位单元被布置成具有特征密度的阵列。 阵列的一个或多个边缘由第一边缘子阵列界定，该第一边缘子阵列的特征密度小于阵列的特征密度。 第一边缘子阵列由第二边缘子阵列邻接，第二边缘子阵列的特征密度小于第一边缘子阵列的特征密度，并且接近背景电路的特征密度。

公开(公告)号：US12047075B2

公开(公告)日：2024-07-23

申请号：US17837960

申请日：2022-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Ho Chang ,  Jaw-Juinn Horng ,  Yung-Chow Peng

IPC: H03K3/013 ,  H03K3/023

CPC classification number: H03K3/013 ,  H03K3/023

Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

公开(公告)号：US11082035B1

公开(公告)日：2021-08-03

申请号：US17030160

申请日：2020-09-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Peng Hsieh ,  Chih-Chiang Chang ,  Yung-Chow Peng

IPC: H03K5/14 ,  H03K5/24 ,  H03K5/134 ,  H03K5/131

Abstract: A digitally controlled delay line (DCDL) includes an input terminal, an output terminal, and a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal. Each stage of the plurality of stages includes first and second inverters configured to selectively propagate the signal along the first signal path, third and fourth inverters configured to selectively propagate the signal along the second signal path, and a fifth inverter configured to selectively propagate the signal from the first signal path to the second signal path.

公开(公告)号：US20210123816A1

公开(公告)日：2021-04-29

申请号：US17140722

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Lin LIU ,  Jaw-Juinn Horng ,  Yung-Chow Peng

IPC: G01K7/21 ,  G01K7/20

Abstract: A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.

公开(公告)号：US10514417B2

公开(公告)日：2019-12-24

申请号：US16291793

申请日：2019-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Zeng Kang ,  Chih-Hsien Chang ,  Wen-Shen Chou ,  Yung-Chow Peng

IPC: G06F17/50 ,  G01R31/28 ,  H03K3/03 ,  H03K19/20

Abstract: An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.

公开(公告)号：US10281501B2

公开(公告)日：2019-05-07

申请号：US15628393

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tao Yang ,  Wen-Shen Chou ,  Yung-Chow Peng

IPC: G01R19/04 ,  G01R31/26 ,  H03L7/18 ,  H03J3/12 ,  H04L27/20 ,  G01R31/28

Abstract: A peak current evaluation apparatus for an IC is provided. The peak current evaluation apparatus includes a pulse tuner and a testing circuit. The pulse tuner receives a clock signal, adjusts pulse width and duty ratio of the clock signal according to at least one predetermined parameter in order to generate a pulse signal with a stress voltage. The testing circuit is coupled to the pulse tuner. The testing circuit, which includes two input ports, receives the pulse signal at one of the two input ports in order to stress a testing device, measures the resistance value of the testing device, and calculates the peak current of the testing device when the resistance value increases and exceeds a threshold value.

公开(公告)号：US09659919B2

公开(公告)日：2017-05-23

申请号：US14578690

申请日：2014-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chow Peng ,  Jaw-Juinn Horng ,  Szu-Lin Liu ,  Po-Zeng Kang

IPC: H01L29/06 ,  H01L27/02 ,  G06F17/50 ,  H01L25/00

CPC classification number: H01L27/0207 ,  G06F17/5063 ,  G06F17/5068 ,  G06F17/5081 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some embodiments, an integrated circuit includes a central array region having a first layout feature density. A background region surrounds the central array region and has a second layout feature density, which is different from the first density. A peripheral array region surrounds the central array region and separates the central array region from the background region. The peripheral array region has a third layout feature density between the first and second layout feature densities.

公开(公告)号：US09378314B2

公开(公告)日：2016-06-28

申请号：US14467327

申请日：2014-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Amit Kundu ,  Jaw-Juinn Horng ,  Yung-Chow Peng ,  Shih-Cheng Yang ,  Chung-Kai Lin

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5036 ,  G06F17/5072 ,  G06F2217/10 ,  G06F2217/78 ,  H01L27/0207

Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.

Abstract translation: 一种用于设计集成电路并预测金属氧化物半导体（MOS）阵列中的电流失配的系统和方法。 选择MOS阵列中的单元的第一子集，并且对这些单元中的每一个进行电流测量。 相对于参考单元的电流确定单元的第一子集中的每个单元的电流的标准偏差。 可以使用确定的第一子集中的一个或多个单元的电流的标准偏差来确定局部变化的标准偏差。 然后可以确定由阵列的x和/或y方向由例如多晶密度梯度效应引起的变化的标准偏差，并且由阵列确定阵列中的任何单元的电流失配。