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公开(公告)号：US11579648B2
公开(公告)日：2023-02-14
申请号：US17535206
申请日：2021-11-24
发明人： Haruki Mori , Hidehiro Fujiwara , Zhi-Hao Chang , Yangsyu Lin , Yu-Hao Hsu , Yen-Huei Chen , Hung-Jen Liao , Chiting Cheng
IPC分类号： G05F1/10 , G05F3/24 , G06F1/28 , H01L27/092 , H01L23/528
摘要： Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
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公开(公告)号：US20220359001A1
公开(公告)日：2022-11-10
申请号：US17814700
申请日：2022-07-25
IPC分类号： G11C11/419 , G11C11/418
摘要： A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
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公开(公告)号：US11450605B2
公开(公告)日：2022-09-20
申请号：US17173750
申请日：2021-02-11
发明人： Chien-Yuan Chen , Cheng-Hung Lee , Hung-Jen Liao , Hau-Tai Shieh , Kao-Cheng Lin , Wei-Min Chan
IPC分类号： H01L23/528 , H01L27/11 , H01L27/092 , G06F30/392 , H01L21/8238
摘要： Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
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44.发明授权公开(公告)号：US11264081B1
公开(公告)日：2022-03-01
申请号：US17006882
申请日：2020-08-30
发明人： Hua-Hsin Yu , Cheng-Hung Lee , Hung-Jen Liao , Hau-Tai Shieh
IPC分类号： G11C11/4091 , G11C11/4074 , G11C11/4076 , G11C11/4099 , G11C7/10
摘要： The disclosure is directed to a memory circuit, an electronic device, and a method of operating the memory circuit. According to an exemplary embodiment, the disclosure is directed to a memory circuit which includes not limited to a voltage equalizing circuit configured to equalize and pre-charge a first data line and a second data line to a reference voltage, a sense amplifier circuit configured to sense a binary data based on a relative voltage between the first data line and the second data line, a read-out latch circuit configured to receive the binary data which is to be transmitted to an external controller, and a write circuit configured to receive a first signal of the first data line and a second signal of the second data line so as to write the first signal to a first bit line and the second signal to a second bit line.
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公开(公告)号：US20210201988A1
公开(公告)日：2021-07-01
申请号：US17201636
申请日：2021-03-15
发明人： Hua-Hsin Yu , Cheng Hung Lee , Hung-Jen Liao , Hau-Tai Shieh
IPC分类号： G11C11/412 , G11C11/419
摘要： A latch formed from a memory cell includes a clock input terminal configured to receive a clock signal, complementary first and second data terminals, and a latch circuit. The latch circuit has first and second inverters. The first inverter has an input terminal coupled to the first data terminal, and the second inverter has an input terminal coupled to the second data terminal. A first pass gate transistor is coupled between an output terminal of the second inverter and the first data terminal. A second pass gate transistor is coupled between an output terminal of the first inverter and the second data terminal. The first and second pass gate transistors each have a gate terminal coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter.
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46.发明授权公开(公告)号：US10991420B2
公开(公告)日：2021-04-27
申请号：US16991449
申请日：2020-08-12
IPC分类号： G11C11/4094 , G11C7/12 , G11C11/4096
摘要： A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.
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公开(公告)号：US10964683B2
公开(公告)日：2021-03-30
申请号：US15904959
申请日：2018-02-26
发明人： Hidehiro Fujiwara , Hung-Jen Liao , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Sahil Preet Singh
IPC分类号： H01L27/02 , H01L27/11 , H01L23/522 , G11C5/06 , G11C7/18
摘要： A memory array includes a column of cells arranged along a first direction and a bit line extending along the first direction over the column of cells. The column of cells includes a set of memory cells and a set of strap cells. The bit line includes a first conductor in a second conductor. The first conductor extends in the first direction and is in a first conductive layer. The second conductor extends in the first direction and is in a second conductive layer different from the first conductive layer.
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公开(公告)号：US10783955B2
公开(公告)日：2020-09-22
申请号：US16207030
申请日：2018-11-30
发明人： Hidehiro Fujiwara , Li-Wen Wang , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L27/11 , G11C11/419 , G11C11/418 , H01L27/02 , G11C8/14
摘要： A circuit includes a column of memory cells, a first read data line coupled exclusively with a first subset of memory cells of the column of memory cells, a second read data line coupled exclusively with a second subset of memory cells of the column of memory cells, and a plurality of read word lines. Each read word line of the plurality of read word lines is coupled with a memory cell of the first subset of memory cells and with a memory cell of the second subset of memory cells.
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公开(公告)号：US10778198B2
公开(公告)日：2020-09-15
申请号：US16842910
申请日：2020-04-08
发明人： Chien-Yuan Chen , Cheng Hung Lee , Hung-Jen Liao , Hau-Tai Shieh
IPC分类号： H03K3/356 , G11C11/56 , H03K17/687 , H03K19/0185
摘要： A level shifter includes: an input terminal configured to receive an input signal in a first voltage domain; a first output terminal; a second output terminal; a first inverter configured to receive and shift the input signal to a first output signal at the first output terminal in a second voltage domain higher than the first voltage domain in response to a logical high state of an enable signal in the first voltage domain; a second inverter configured to receive and shift a complement of the input signal to a second output signal at the second output terminal in the second voltage domain in response to the logical high state; a pair of NMOS sensing transistors; a PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the enable signal.
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公开(公告)号：US20200235724A1
公开(公告)日：2020-07-23
申请号：US16842910
申请日：2020-04-08
发明人： Chien-Yuan Chen , Cheng Hung Lee , Hung-Jen Liao , Hau-Tai Shieh
IPC分类号： H03K3/356 , H03K19/0185 , H03K17/687 , G11C11/56
摘要： A level shifter includes: an input terminal configured to receive an input signal in a first voltage domain; a first output terminal; a second output terminal; a first inverter configured to receive and shift the input signal to a first output signal at the first output terminal in a second voltage domain higher than the first voltage domain in response to a logical high state of an enable signal in the first voltage domain; a second inverter configured to receive and shift a complement of the input signal to a second output signal at the second output terminal in the second voltage domain in response to the logical high state; a pair of NMOS sensing transistors; a PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the enable signal.
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