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52 条记录 (耗时 0.024 秒)

    Electrical Interconnect Using Locally Conductive Adhesive
    41.
    发明申请
    Electrical Interconnect Using Locally Conductive Adhesive 有权
    电气互连使用局部导电粘合剂

    公开(公告)号：US20080093019A1

    公开(公告)日：2008-04-24

    申请号：US11960034

    申请日：2007-12-19

    申请人： Chad Cobbley ,  Steve Heppler

    发明人： Chad Cobbley ,  Steve Heppler

    IPC分类号： B29C65/52

    CPC分类号： H05K3/323 ,  C08K7/16 ,  C08K9/00 ,  C09J5/00 ,  C09J9/02 ,  C09J11/08 ,  C09J2205/11 ,  H01R4/04 ,  H05K3/321 ,  H05K2201/0224 ,  H05K2203/0278 ,  H05K2203/1163 ,  Y10T428/25 ,  Y10T428/263 ,  Y10T428/2982 ,  Y10T428/2989 ,  Y10T428/2991 ,  Y10T428/2998

    摘要： An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.

    摘要翻译： 公开了一种各向异性导电互连件，其中包含具有至少一种非导电材料的可破坏涂层的颗粒的粘合剂在第一接触和第二接触之间被压缩。 对两个触点的压缩使可破坏的涂层暴露出与第一和第二触点接触的导电材料。 导电材料可以是金属导体或两部分反应性导电树脂/催化剂体系。 还公开了用于制造用于制造电互连的这种电互连和粘合剂的方法。

    Molded stiffener for thin substrates
    42.
    发明申请
    Molded stiffener for thin substrates 审中-公开

    公开(公告)号：US20060290011A1

    公开(公告)日：2006-12-28

    申请号：US11513791

    申请日：2006-08-31

    申请人： Chad Cobbley ,  Cary Baerlocher

    发明人： Chad Cobbley ,  Cary Baerlocher

    IPC分类号： H01L23/28

    CPC分类号： H01L23/3121 ,  H01L21/565 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/49558 ,  H01L24/32 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

    摘要： A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is molded to the substrate to provide rigidity and support to the substrate. The stiffener material can comprise a polymeric material molded to the substrate by a molding technique such as transfer molding, injection molding, and spray molding, or using an encapsulating material. One or more dies, chips, or other semiconductor or microelectronic devices can be disposed on the substrate to form a die assembly. The stiffener can be molded to a substrate comprising one or more dies, over which an encapsulating material can be applied to produce a semiconductor die package.

    Molded stiffener for thin substrates
    48.
    发明申请
    Molded stiffener for thin substrates 有权
    用于薄基材的成型加强件

    公开(公告)号：US20050029549A1

    公开(公告)日：2005-02-10

    申请号：US10932940

    申请日：2004-09-02

    申请人： Chad Cobbley ,  Cary Baerlocher

    发明人： Chad Cobbley ,  Cary Baerlocher

    IPC分类号： H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/495 ,  H01L27/10

    CPC分类号： H01L23/3121 ,  H01L21/565 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/49558 ,  H01L24/32 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

    摘要： A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is molded to the substrate to provide rigidity and support to the substrate. The stiffener material can comprise a polymeric material molded to the substrate by a molding technique such as transfer molding, injection molding, and spray molding, or using an encapsulating material. One or more dies, chips, or other semiconductor or microelectronic devices can be disposed on the substrate to form a die assembly. The stiffener can be molded to a substrate comprising one or more dies, over which an encapsulating material can be applied to produce a semiconductor die package.

    摘要翻译： 提供了模制到诸如引线框架的半导体衬底的加强件以及将加强件模制到基底的方法。 加强件被模制到基底上以为基底提供刚性和支撑。 加强材料可以包括通过模制技术（例如传递模塑，注模和喷射模制）或使用封装材料模制到基底上的聚合物材料。 可以在衬底上设置一个或多个管芯，芯片或其它半导体或微电子器件以形成管芯组件。 加强件可以模制到包括一个或多个管芯的基底上，在其上可以施加封装材料以制造半导体管芯封装。

    Method for in-line testing of flip-chip semiconductor assemblies
    49.
    发明申请
    Method for in-line testing of flip-chip semiconductor assemblies 失效

    公开(公告)号：US20050024080A1

    公开(公告)日：2005-02-03

    申请号：US10927546

    申请日：2004-08-25

    申请人： Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

    发明人： Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

    IPC分类号： G01R1/04 ,  G01R31/26

    CPC分类号： G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

    摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    Method for in-line testing of flip-chip semiconductor assemblies
    50.
    发明申请
    Method for in-line testing of flip-chip semiconductor assemblies 失效

    公开(公告)号：US20050007141A1

    公开(公告)日：2005-01-13

    申请号：US10900609

    申请日：2004-07-27

    申请人： Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

    发明人： Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

    IPC分类号： G01R1/04 ,  G01R31/26

    CPC分类号： G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

    摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.