公开(公告)号：US20170374736A1

公开(公告)日：2017-12-28

申请号：US15698426

申请日：2017-09-07

申请人： Ares Materials, Inc.

发明人： Radu REIT ,  David ARREAGA-SALAS

IPC分类号： H05K1/02 ,  H05K1/03 ,  H05K3/00

CPC分类号： H05K1/0283 ,  H01L27/1218 ,  H01L51/0097 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/0014 ,  H05K3/0023 ,  H05K3/0055 ,  H05K2201/0141 ,  H05K2201/0187 ,  H05K2203/0143 ,  H05K2203/0796 ,  H05K2203/095 ,  H05K2203/1163 ,  H05K2203/1194 ,  H05K2203/1476 ,  H05K2203/1545

摘要： A bulk substrate for stretchable electronics. The bulk substrate is manufactured with a process that forms a soft-elastic region of the bulk substrate. The soft-elastic region includes a strain capacity of greater than or equal to 25% and a first Young's modulus below 10% of a maximum local modulus of the bulk substrate. The process also forms a stiff-elastic region of the bulk substrate. The stiff-elastic region includes a strain capacity of less than or equal to 5% and a second Young's modulus greater than 10% of the maximum local modulus of the bulk substrate.

公开(公告)号：US20140083740A1

公开(公告)日：2014-03-27

申请号：US14123195

申请日：2013-03-22

申请人： SEKISUI CHEMICAL CO., LTD.

发明人： Hideaki Ishizawa ,  Takashi Kubota

IPC分类号： H01B1/20

CPC分类号： H01B1/20 ,  C08G59/5073 ,  C08G59/687 ,  C08K3/10 ,  C08L101/12 ,  H01B1/22 ,  H05K3/3494 ,  H05K2203/1163 ,  C08L63/00

摘要： The present invention provides a conductive material capable of decreasing the connection resistance of a connection structure when the connection structure is obtained by electrically connecting electrodes.The conductive material according to the present invention includes a binder resin and conductive particles each having a solder at a conductive surface, the binder resin includes a curable compound capable of being cured by heating, and a thermal curing agent, and when the binder resin and the solder in the conductive particle are each heated at a temperature rising rate of 10° C./minute to perform differential scanning calorimetry, an exothermic peak top temperature in curing of the binder resin is lower than an endothermic peak top temperature in melting of the solder.

摘要翻译： 本发明提供一种当通过电连接电极获得连接结构时能够降低连接结构的连接电阻的导电材料。 根据本发明的导电材料包括粘合剂树脂和在导电表面上具有焊料的导电颗粒，粘合剂树脂包括能够通过加热固化的固化性化合物和热固化剂，并且当粘合剂树脂和 导电粒子中的焊料各自以10℃/分钟的升温速度进行加热，进行差示扫描量热法，粘合剂树脂固化时的放热峰顶温度低于熔融时的吸热峰顶温度 焊接。

公开(公告)号：US08507076B2

公开(公告)日：2013-08-13

申请号：US13207981

申请日：2011-08-11

申请人： Keiichi Nakao ,  Yukihiro Shimasaki ,  Atsushi Iwase ,  Koji Shimoyama

发明人： Keiichi Nakao ,  Yukihiro Shimasaki ,  Atsushi Iwase ,  Koji Shimoyama

IPC分类号： B41M5/00

CPC分类号： H01G4/12 ,  H01G4/0085 ,  H01G13/00 ,  H01L21/4867 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/1208 ,  H05K3/125 ,  H05K3/386 ,  H05K2203/013 ,  H05K2203/0783 ,  H05K2203/1163 ,  Y10T29/49133 ,  Y10T428/24802 ,  Y10T428/24893 ,  Y10T428/2495 ,  Y10T428/24975 ,  Y10T428/25 ,  Y10T428/265

摘要： A base layer is formed on the surface of metal plate, metal pipe, unbaked ceramic sheet, laminated ceramic green sheet, etc., the base layer causing a gelling reaction with inkjet-ink. The base layer improves ink acceptability for low viscosity inks such as inkjet-ink, and prevents oozing, draining, uneven thickness of an ink pattern and a resist pattern. Thus, the present invention enables to use an ink jet process for providing resist patterns for etching, etc., which has to fulfill stringent high precision requirements.

摘要翻译： 在金属板，金属管，未烘烤陶瓷片，层压陶瓷生片等的表面上形成基层，基层与喷墨油墨发生胶凝反应。 基层改善了低粘度油墨如喷墨油墨的油墨可接受性，并且防止油墨图案的渗出，排水，厚度不均匀和抗蚀剂图案。 因此，本发明能够使用喷墨方法来提供必须满足严格的高精度要求的用于蚀刻的抗蚀剂图案等。

公开(公告)号：US08492653B2

公开(公告)日：2013-07-23

申请号：US12922720

申请日：2009-03-12

申请人： Gereon Vogtmeier

发明人： Gereon Vogtmeier

IPC分类号： H01R4/24

CPC分类号： H01R4/04 ,  H01R4/24 ,  H01R12/61 ,  H01R13/03 ,  H01R13/22 ,  H01R13/717 ,  H05K3/321 ,  H05K3/361 ,  H05K2201/10378 ,  H05K2203/0278 ,  H05K2203/1105 ,  H05K2203/1163 ,  Y10T29/49174

摘要： Provided is a connector (200; 700) for establishing an electrical connection with a conductive tape (100). The conductive tape comprises at least a first conducting layer (104) and an insulating layer (102). The connector comprises a first conductive region (204; 710) and a first connection region (712). The first connection region (712) is adapted to establish an electrical connection between the first conducting layer (104) of the conducting tape and the first conductive region (204; 110) when a perturbation is applied. The perturbation may be the application of pressure or temperature to the connector.

摘要翻译： 提供了一种用于与导电带（100）建立电连接的连接器（200; 700）。 导电带至少包括第一导电层（104）和绝缘层（102）。 连接器包括第一导电区域（204; 710）和第一连接区域（712）。 当施加扰动时，第一连接区域（712）适于在导电带的第一导电层（104）和第一导电区域（204; 110）之间建立电连接。 扰动可能是对连接器施加压力或温度。

公开(公告)号：US08322027B1

公开(公告)日：2012-12-04

申请号：US11926498

申请日：2007-10-29

申请人： Robert J. Greenberg ,  Neil Hamilton Talbot ,  Jordan Matthew Neysmith ,  Jerry Ok

发明人： Robert J. Greenberg ,  Neil Hamilton Talbot ,  Jordan Matthew Neysmith ,  Jerry Ok

IPC分类号： H05K3/00 ,  H05K3/10 ,  H05K1/00

CPC分类号： H05K3/06 ,  A61N1/0543 ,  H05K1/118 ,  H05K3/0041 ,  H05K3/28 ,  H05K3/381 ,  H05K3/388 ,  H05K2201/0154 ,  H05K2201/0317 ,  H05K2203/0554 ,  H05K2203/0789 ,  H05K2203/0793 ,  H05K2203/095 ,  H05K2203/1163 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49155

摘要： A method for manufacturing a flexible circuit electrode array, comprising: a) depositing a metal trace layer containing a base coating layer, a conducting layer and a top coating layer on said insulator polymer base layer; b) applying a layer of photoresist on said metal trace layer and patterning said metal trace layer and forming metal traces on said insulator polymer base layer; c) activating said insulator polymer base layer and depositing a top insulator polymer layer and forming one single insulating polymer layer with said base insulator polymer layer; d) applying a thin metal layer and a layer of photoresist on the surface of said insulator polymer layer and selective etching said insulator layer and said top coating layer to obtain at least one via; and e) filling said via with electrode material. A layer of polymer is laid down. A layer of metal is applied to the polymer and patterned to create electrodes and leads for those electrodes. A second layer of polymer is applied over the metal layer and patterned to leave openings for the electrodes, or openings are created later by means such as laser ablation. Hence the array and its supply cable are formed of a single body. Alternatively, multiple alternating layers of metal and polymer may be applied to obtain more metal traces within a given width.The method provides an excellent adhesion between the polymer base layer and the polymer top layer and insulation of the trace metals and electrodes.

摘要翻译： 一种制造柔性电路电极阵列的方法，包括：a）在所述绝缘体聚合物基底层上沉积包含基底涂层，导电层和顶部涂层的金属迹线层; b）在所述金属迹线层上施加一层光致抗蚀剂，并图案化所述金属迹线层并在所述绝缘体聚合物基底层上形成金属迹线; c）激活所述绝缘体聚合物基层并沉积顶部绝缘体聚合物层并与所述基础绝缘体聚合物层形成单个绝缘聚合物层; d）在所述绝缘体聚合物层的表面上施加薄金属层和光致抗蚀剂层，并选择性地蚀刻所述绝缘体层和所述顶部涂层以获得至少一个通孔; 和e）用电极材料填充所述通孔。 放置一层聚合物。 将一层金属施加到聚合物上并图案化以产生用于那些电极的电极和引线。 将第二层聚合物施加在金属层上并图案化以留下电极的开口，或稍后通过诸如激光烧蚀的手段产生开口。 因此阵列及其供电电缆由单体形成。 或者，可以施加金属和聚合物的多个交替层以在给定宽度内获得更多的金属迹线。 该方法提供了聚合物基底层和聚合物顶层之间的极好的粘合性，并且痕迹金属和电极的绝缘性。

公开(公告)号：US08318585B2

公开(公告)日：2012-11-27

申请号：US12990608

申请日：2009-04-30

申请人： Yasuhide Ohno ,  Keisuke Taniguchi ,  Tatsuya Takeuchi ,  Taizo Hagihara

发明人： Yasuhide Ohno ,  Keisuke Taniguchi ,  Tatsuya Takeuchi ,  Taizo Hagihara

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H05K3/3489 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29109 ,  H01L2224/75 ,  H01L2224/751 ,  H01L2224/7525 ,  H01L2224/757 ,  H01L2224/8101 ,  H01L2224/81011 ,  H01L2224/81022 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2203/1163 ,  H01L2924/0132 ,  H01L2924/00014 ,  H01L2224/83205

摘要： To facilitate bonding of articles at a low temperature without degrading electrical contact between the articles.An oxide film reducing treatment with hydrogen radicals is carried out for surfaces of lead-out electrodes (5) and bump electrodes (6) on the lead-out electrodes (5) of a semiconductor chip (2) and surfaces of lead-out electrodes (8) of an intermediate substrate (3), and, after that, the bump electrodes (6) of the semiconductor chip (2) and the lead-out electrodes (8) of the intermediate substrate (3) are aligned with each other. After that, a pressure is applied to bond the bump electrodes (6) and the lead-out electrodes (8).

摘要翻译： 为了便于物品在低温下的粘合而不降低物品之间的电接触。 对半导体芯片（2）的引出电极（5）的引出电极（5）和凸点电极（6）的表面进行氢自由基的氧化膜还原处理，以及引出电极 （3）的所述半导体芯片（2）的凸起电极（6）和所述中间基板（3）的引出电极（8）彼此对准 。 之后施加压力以接合凸起电极（6）和引出电极（8）。

公开(公告)号：US08178188B2

公开(公告)日：2012-05-15

申请号：US12339826

申请日：2008-12-19

申请人： Keiichi Nakao ,  Yukihiro Shimasaki ,  Atsushi Iwase ,  Koji Shimoyama

发明人： Keiichi Nakao ,  Yukihiro Shimasaki ,  Atsushi Iwase ,  Koji Shimoyama

IPC分类号： B41M5/00 ,  B44C1/17 ,  G03G7/00

CPC分类号： H01G4/12 ,  H01G4/0085 ,  H01G13/00 ,  H01L21/4867 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/1208 ,  H05K3/125 ,  H05K3/386 ,  H05K2203/013 ,  H05K2203/0783 ,  H05K2203/1163 ,  Y10T29/49133 ,  Y10T428/24802 ,  Y10T428/24893 ,  Y10T428/2495 ,  Y10T428/24975 ,  Y10T428/25 ,  Y10T428/265

摘要： A base layer is formed on the surface of metal plate, metal pipe, unbaked ceramic sheet, laminated ceramic green sheet, etc., the base layer causing a gelling reaction with inkjet-ink. The base layer improves ink acceptability for low viscosity inks such as inkjet-ink, and prevents oozing, draining, uneven thickness of an ink pattern and a resist pattern. Thus, the present invention enables to use an ink jet process for providing resist patterns for etching, etc., which has to fulfill stringent high precision requirements.

摘要翻译： 在金属板，金属管，未烘烤陶瓷片，层压陶瓷生片等的表面上形成基层，基层与喷墨油墨发生胶凝反应。 基层改善了低粘度油墨如喷墨油墨的油墨可接受性，并且防止油墨图案的渗出，排水，厚度不均匀和抗蚀剂图案。 因此，本发明能够使用喷墨方法来提供必须满足严格的高精度要求的用于蚀刻的抗蚀剂图案等。

公开(公告)号：US08129823B2

公开(公告)日：2012-03-06

申请号：US11986998

申请日：2007-11-27

申请人： Ravindra V. Tanikella

发明人： Ravindra V. Tanikella

IPC分类号： H01L23/58 ,  H01L23/52

CPC分类号： H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

摘要： Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

摘要翻译： 用于微电子封装的高度可靠的互连。 在一个实施例中，积聚互连中的电介质层具有玻璃化转变温度的等级; 并且稍后施加的电介质层在低于较早施加的电介质层的玻璃化转变温度的温度下被层压。 在一个实施方案中，通过热固化工艺增加了积聚互连中早期施加的介电膜的玻璃化转变温度，以超过用于层压后来施加的电介质膜的温度。 在一个实施方案中，在层压聚酰亚胺材料的膜（例如通过催化剂的密封剂的光化学或热降解）之后，形成具有嵌入催化剂以促进交联的聚酰亚胺材料。 在一个实施例中，阻焊剂开口壁具有通过激光辅助接种产生的可湿性层，使得阻焊剂开口壁之间没有间隙，并且在阻焊剂开口中没有底部填充物。

公开(公告)号：US20110089462A1

公开(公告)日：2011-04-21

申请号：US12674804

申请日：2008-08-29

申请人： David Van Heerden ,  Timothy Ryan Rude ,  Ramzi Vincent

发明人： David Van Heerden ,  Timothy Ryan Rude ,  Ramzi Vincent

IPC分类号： H01L33/48 ,  H01L21/60 ,  H01L31/00

CPC分类号： H01L24/83 ,  H01L24/33 ,  H01L31/02002 ,  H01L33/62 ,  H01L2224/33104 ,  H01L2224/335 ,  H01L2224/80359 ,  H01L2224/83024 ,  H01L2224/83095 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83232 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/0203 ,  H05K1/056 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/10106 ,  H05K2201/10689 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10969 ,  H05K2203/0278 ,  H05K2203/0405 ,  H05K2203/1163 ,  Y02P70/613 ,  Y10S362/80 ,  H01L2924/00

摘要： A method for bonding an LED assembly (71) or other electronic package (31) to a substrate PCB containing a heat-sink (52), which utilizes layers of reactive multilayer foil (51) disposed between contacts (32, 34) of the electronic package 31 and the associated contact pads (55) on the supporting substrate PCB. By initiating an exothermic reaction in the reactive multilayer foil (51), together with an application of pressure, sufficient heat is generated between the contacts (32, 34) and the associated contact pads (55) to melt adjacent bonding material (54) to obtain good electrically and thermally conductive bonds between the contacts 32, 34 and contact pads (55) without thermally damaging the electronic package (31), heat-sensitive components (35) associated with the electronic package (31), or other the supporting substrate PCB.

摘要翻译： 一种用于将LED组件（71）或其它电子封装（31）接合到包含散热器（52）的基板PCB的方法，所述基板PCB利用设置在所述散热器（52）的触点（32,34）之间的反应性多层箔（51） 电子封装31和支撑基板PCB上的相关接触焊盘（55）。 通过在反应性多层箔（51）中引发放热反应以及施加压力，在触头（32,34）和相关联的接触垫（55）之间产生足够的热量以将相邻的接合材料（54）熔化成 在电子封装（31），与电子封装（31）相关联的热敏元件（35）或其他支撑衬底（31）之间，在触点32,34和接触焊盘（55）之间获得良好的导电和导热接合， PCB。

公开(公告)号：US20090314527A1

公开(公告)日：2009-12-24

申请号：US12485957

申请日：2009-06-17

申请人： Kaoru HATANO ,  Akihiro CHIDA ,  Takaaki NAGATA ,  Masayuki SAKAKURA

发明人： Kaoru HATANO ,  Akihiro CHIDA ,  Takaaki NAGATA ,  Masayuki SAKAKURA

IPC分类号： H05K1/03 ,  H05K1/16 ,  B05D5/12 ,  H01L21/50

CPC分类号： H01L27/1266 ,  G06K19/07745 ,  G06K19/07747 ,  G06K19/07749 ,  G06K19/0775 ,  H01L21/6835 ,  H01L23/145 ,  H01L23/49827 ,  H01L23/5389 ,  H01L27/1218 ,  H01L2221/6835 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H05K1/0366 ,  H05K3/002 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2203/1163 ,  Y10T29/49126 ,  Y10T29/49169 ,  H01L2924/00

摘要： To form a conductive region in a prepreg without opening a through hole in a fibrous body. A wiring substrate is provided, including: an organic resin layer and a fibrous body, wherein the fibrous body is impregnated with the organic resin layer; and a wiring with which the fibrous body is impregnated and which is formed by dissolving the organic resin layer. The wiring is exposed on both surfaces of the organic resin layer and penetrates the fibrous body so that the fibrous body is positioned in the through wiring. Further, a semiconductor device is provided by adhering an integrated circuit chip having a bump to the wiring substrate so that the bump is in contact with the wiring.

摘要翻译： 在预浸料坯中形成导电区域，而不在纤维体内打开通孔。 提供一种布线基板，包括：有机树脂层和纤维体，其中所述纤维体浸渍有机树脂层; 以及纤维体浸渍并通过溶解有机树脂层而形成的布线。 布线暴露在有机树脂层的两个表面上并穿透纤维体，使得纤维体位于贯通布线中。 此外，通过将具有凸块的集成电路芯片粘附到布线基板以使得凸块与布线接触来提供半导体器件。