公开(公告)号：US20070034985A1

公开(公告)日：2007-02-15

申请号：US11502387

申请日：2006-08-11

申请人： Tomoko Matsudai ,  Norio Yasuhara

发明人： Tomoko Matsudai ,  Norio Yasuhara

IPC分类号： H01L23/58

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.

摘要翻译： 一种半导体器件，包括：选择性地形成在半导体衬底之上的第一导电类型的基极层; 经由所述绝缘膜形成在所述基底层上的栅电极; 选择性地形成在所述基极层的所述栅电极的一侧的表面处的第二导电类型的源极层; 沟道注入层，其选择性地形成在所述基底层的表面处以与所述栅极电极下方的源极层相邻，所述沟道注入层具有比所述基底层更高的浓度; 所述第二导电类型的RESURF层选择性地形成在所述基极层的所述栅极电极的另一侧的表面处; 以及与RESURF层相邻的第二导电类型的漏极层，所述漏极层的一部分与所述基极层重叠，并且所述漏极层具有比所述RESURF层更高的浓度。

公开(公告)号：US08502309B2

公开(公告)日：2013-08-06

申请号：US12645072

申请日：2009-12-22

申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

公开(公告)号：US20110233668A1

公开(公告)日：2011-09-29

申请号：US13053063

申请日：2011-03-21

申请人： Manji OBATAKE ,  Tomoko Matsudai

发明人： Manji OBATAKE ,  Tomoko Matsudai

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/7835

摘要： According to one embodiment, a semiconductor device includes a base region of a second conductivity type, a drift region of a first conductivity type, an insulating layer, a drain region of the first conductivity type, a gate oxide film, a gate electrode, a first main electrode, and a second main electrode. The base region includes a source region of the first conductivity type. The drift region is adjacent to the base region. The insulating layer is provided from a surface to inside of the drift region. The drain region is provided in the surface of the drift region and opposed to the source region across the base region and the insulating layer. The gate oxide film is provided on a surface of the base region. The gate electrode is provided on the gate oxide film. The first main electrode is connected to the source region. The second main electrode is connected to the drain region. As viewed in a direction perpendicular to the surface of the base region, the source region and at least a part of the drain region extend generally parallel in a line shape, and a length of a portion of the drift region sandwiched between the insulating layer and the base region is shorter in the generally parallel extending direction than in a direction generally perpendicular to the generally parallel extending direction.

摘要翻译： 根据一个实施例，半导体器件包括第二导电类型的基极区域，第一导电类型的漂移区域，绝缘层，第一导电类型的漏极区域，栅极氧化物膜，栅电极， 第一主电极和第二主电极。 基极区域包括第一导电类型的源极区域。 漂移区域与基底区域相邻。 绝缘层从漂移区域的表面到内部提供。 漏极区域设置在漂移区域的表面中，并且跨越基极区域和绝缘层与源极区域相对。 栅极氧化膜设置在基极区域的表面上。 栅电极设置在栅氧化膜上。 第一主电极连接到源区。 第二主电极连接到漏区。 从与基底区域的表面垂直的方向观察，源极区域和漏极区域的至少一部分大致平行地呈直线状延伸，漂移区域的一部分的长度夹在绝缘层和 基本区域在大致平行的延伸方向上比在大致垂直于大致平行的延伸方向的方向上更短。

公开(公告)号：US07998849B2

公开(公告)日：2011-08-16

申请号：US12716352

申请日：2010-03-03

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

IPC分类号： H01L21/336

CPC分类号： H01L29/1045 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7838

摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

摘要翻译： 在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。 第一导电类型的源区形成在高电阻层的表面区域上。 第一导电类型的漏极区域形成在与源极区域一定距离处。 在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。 在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。 栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。 栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

公开(公告)号：US07646059B2

公开(公告)日：2010-01-12

申请号：US11501715

申请日：2006-08-10

申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

公开(公告)号：US20070040216A1

公开(公告)日：2007-02-22

申请号：US11505337

申请日：2006-08-17

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

IPC分类号： H01L29/76

CPC分类号： H01L29/1045 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7838

摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

摘要翻译： 在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。 第一导电类型的源区形成在高电阻层的表面区域上。 第一导电类型的漏极区域形成在与源极区域一定距离处。 在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。 在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。 栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。 栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

公开(公告)号：US08981473B2

公开(公告)日：2015-03-17

申请号：US13410739

申请日：2012-03-02

申请人： Ryo Wada ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

发明人： Ryo Wada ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

IPC分类号： H01L29/78 ,  H01L21/761 ,  H01L29/739 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L21/761 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66128 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611 ,  Y10S257/91

摘要： According to one embodiment, in a dielectric isolation substrate, an insulating film having a first thickness is provided on a semiconductor substrate. A semiconductor layer of a first conductivity type having a second thickness is provided on the insulating film. An impurity diffusion layer of a second conductivity type is provided partially in a lower portion of the semiconductor layer and is in contact with the insulating film.

摘要翻译： 根据一个实施例，在绝缘隔离衬底中，在半导体衬底上设置具有第一厚度的绝缘膜。 具有第二厚度的第一导电类型的半导体层设置在绝缘膜上。 第二导电类型的杂质扩散层部分地设置在半导体层的下部并与绝缘膜接触。

公开(公告)号：US08637928B2

公开(公告)日：2014-01-28

申请号：US13053063

申请日：2011-03-21

申请人： Manji Obatake ,  Tomoko Matsudai

发明人： Manji Obatake ,  Tomoko Matsudai

IPC分类号： H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/7835

摘要： According to one embodiment, a semiconductor device includes a base region of a second conductivity type, a drift region of a first conductivity type, an insulating layer, a drain region of the first conductivity type, a gate oxide film, a gate electrode, a first main electrode, and a second main electrode. The base region includes a source region of the first conductivity type. The drift region is adjacent to the base region. The insulating layer is provided from a surface to inside of the drift region. The drain region is provided in the surface of the drift region and opposed to the source region across the base region and the insulating layer. The gate oxide film is provided on a surface of the base region. The gate electrode is provided on the gate oxide film. The first main electrode is connected to the source region. The second main electrode is connected to the drain region. As viewed in a direction perpendicular to the surface of the base region, the source region and at least a part of the drain region extend generally parallel in a line shape, and a length of a portion of the drift region sandwiched between the insulating layer and the base region is shorter in the generally parallel extending direction than in a direction generally perpendicular to the generally parallel extending direction.

摘要翻译： 根据一个实施例，半导体器件包括第二导电类型的基极区域，第一导电类型的漂移区域，绝缘层，第一导电类型的漏极区域，栅极氧化物膜，栅电极， 第一主电极和第二主电极。 基极区域包括第一导电类型的源极区域。 漂移区域与基底区域相邻。 绝缘层从漂移区域的表面到内部提供。 漏极区域设置在漂移区域的表面中，并且跨越基极区域和绝缘层与源极区域相对。 栅极氧化膜设置在基极区域的表面上。 栅电极设置在栅氧化膜上。 第一主电极连接到源区。 第二主电极连接到漏区。 从与基底区域的表面垂直的方向观察，源极区域和漏极区域的至少一部分大致平行地呈直线状延伸，漂移区域的一部分的长度夹在绝缘层和 基本区域在大致平行的延伸方向上比在大致垂直于大致平行的延伸方向的方向上更短。

公开(公告)号：US20130049111A1

公开(公告)日：2013-02-28

申请号：US13410739

申请日：2012-03-02

申请人： Ryo WADA ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

发明人： Ryo WADA ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L21/761 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66128 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611 ,  Y10S257/91

摘要： According to one embodiment, in a dielectric isolation substrate, an insulating film having a first thickness is provided on a semiconductor substrate. A semiconductor layer of a first conductivity type having a second thickness is provided on the insulating film. An impurity diffusion layer of a second conductivity type is provided partially in a lower portion of the semiconductor layer and is in contact with the insulating film.

摘要翻译： 根据一个实施例，在绝缘隔离衬底中，在半导体衬底上设置具有第一厚度的绝缘膜。 具有第二厚度的第一导电类型的半导体层设置在绝缘膜上。 第二导电类型的杂质扩散层部分地设置在半导体层的下部并与绝缘膜接触。

公开(公告)号：US08362554B2

公开(公告)日：2013-01-29

申请号：US12878979

申请日：2010-09-09

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Takashi Tsurugai ,  Kumiko Sato

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Takashi Tsurugai ,  Kumiko Sato

IPC分类号： H01L29/78

CPC分类号： H01L29/0692 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835

摘要： According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.

摘要翻译： 根据一个实施例，半导体器件包括漏极区，源极区，沟道区，绝缘膜，栅电极，第一半导体区和第二半导体区。 源极区包括第一导电类型的源极层，第二导电类型的第一背栅极层和第二导电类型的第二背栅极层。 第一背栅层在沟道长度方向的一侧与第二半导体区相邻，并且在沟道长度方向的另一侧与源极相邻。 第二背栅层在沟道长度方向的一侧与源极层相邻，并且与沟道长度方向的另一侧的第二半导体区域相邻。