公开(公告)号：US06565759B1

公开(公告)日：2003-05-20

申请号：US09375203

申请日：1999-08-16

申请人： Bi-Ling Chen ,  Erik S. Jeng ,  Hao-Chieh Liu

发明人： Bi-Ling Chen ,  Erik S. Jeng ,  Hao-Chieh Liu

IPC分类号： H01G900

CPC分类号： H01L21/02274 ,  H01L21/02129 ,  H01L21/31116 ,  H01L21/31625

摘要： A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled by controlling the gas composition. There is provided a silicon substrate formed upon it a patterned microelectronics layer over which is formed a silicon containing dielectric layer. There is placed the silicon substrate within a reactor chamber equipped with electrodes which is evacuated. There is then filled the reactor chamber with a reactive gas mixture consisting of an oxidizing gas and two reactive gases. There may be optionally included in the reactive gas mixture nitrogen and inert gases for control purposes, but excluded from the reactive gas mixture are oxidizing gases containing carbon and oxygen. There is then formed a plasma by supplying high frequency electrical energy to the electrodes within the reactor chamber to bring about a plasma activated reactive gas etching environment, where the conditions may be selected to optimize the desired etch rate and etch rate selectivity.

摘要翻译： 在采用等离子体激活的反应气体混合物的基板上蚀刻含硅介质层内的图案的方法，其中层材料蚀刻速率，蚀刻速率比和通过控制气体成分控制的图案纵横比。 提供了在其上形成图案化的微电子层的硅衬底，在其上形成含硅介电层。 将硅衬底放置在配备有被抽真空的电极的反应器室内。 然后用反应气体混合物填充反应器室，该气体混合物由氧化气体和两种反应性气体组成。 为了控制目的，反应气体混合物中可以任选地包含氮气和惰性气体，但是从反应性气体混合物排除的是含有碳和氧的氧化气体。 然后通过向反应器室内的电极提供高频电能来形成等离子体，以产生等离子体激活的反应气体蚀刻环境，其中可以选择条件以优化所需的蚀刻速率和蚀刻速率选择性。

公开(公告)号：US06239011B1

公开(公告)日：2001-05-29

申请号：US09089557

申请日：1998-06-03

申请人： Bi-Ling Chen ,  Erik S. Jeng

发明人： Bi-Ling Chen ,  Erik S. Jeng

IPC分类号： H01L21306

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76897

摘要： The practice of forming self-aligned contacts (SACs) in MOSFETs using a silicon nitride gate sidewall and a silicon nitride gate cap has found wide acceptance, particularly in the manufacture of DRAMs, where bitline contacts are formed between two adjacent wordlines, each having a nitride sidewall. The contact etch requires a an RIE etch having a high oxide/nitride selectivity. In order to etch SACs having widths of less than 0.35 microns at their base, such as are encountered in high density DRAMs, special steps must be taken to prevent polymer bridging across the opening which leaves residual insulative material at the base of the contact. The problem is further complicated when the insulative layer through which the opening is formed comprises a silicate glass such as BPSG over a silicon oxide layer. The invention discloses the use of an etchant gas mixture containing octafluorocyclobutane and CH3F in combination with a small but critical concentration of oxygen to etch the SAC opening cleanly and without deleterious erosion of silicon nitride sidewall insulation. The added oxygen prevents polymer bridging across the narrow portion of the SAC.

摘要翻译： 在使用氮化硅栅极侧壁和氮化硅栅极帽的MOSFET中形成自对准触点（SAC）的做法已经被广泛接受，特别是在DRAM的制造中，其中在两个相邻字线之间形成位线触点，每个具有 氮化物侧壁。 接触蚀刻需要具有高氧化物/氮化物选择性的RIE蚀刻。 为了在其底部蚀刻具有小于0.35微米的宽度的SAC，例如在高密度DRAM中遇到的，必须采取特殊步骤以防止聚合物桥接穿过开口，从而在接触的基部留下残留的绝缘材料。 当形成开口的绝缘层在氧化硅层上包含诸如BPSG的硅酸盐玻璃时，问题更加复杂。 本发明公开了含有八氟环丁烷和CH 3 F的蚀刻剂气体混合物与小但临界浓度的氧的组合在蚀刻SAC开口并且没有氮化硅侧壁绝缘的有害侵蚀的用途。 添加的氧阻止聚合物桥接跨越SAC的窄部分。

公开(公告)号：US06177695B1

公开(公告)日：2001-01-23

申请号：US09414099

申请日：1999-10-07

申请人： Erik S. Jeng

发明人： Erik S. Jeng

IPC分类号： H01L27108

CPC分类号： H01L27/10888 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

摘要： The conventional capacitor-under-bitline (CUB) DRAM structure faces problems of high photoresist developing aspect ratio and step-height. The present invention discloses a DRAM with planar upper-plate structure and the upper-plate forms an opening broader than the bitline contacts at the top of the lower-plate neighboring the bitline contacts to isolate from the bitline contacts, and the step height at the interface between the peripheral circuit and cell arrays almost does not exist. Furthermore, conventional problems could be solved because of an oxide plug during producing bitline contacts and the thick oxide deposited on the peripheral circuit. A lightly doped polysilicon is deposited between the lower-plate and the silicon wafer substrate to avoid current leakage of the lower-plate.

摘要翻译： 常规的电容器下位线（CUB）DRAM结构面临高光致抗蚀剂显影纵横比和步长的问题。 本发明公开了一种具有平面上板结构的DRAM，并且上板形成的开口宽于与位线触头相邻的下板的顶部处的位线触点，以与位线触头隔离，并且在 外围电路和电池阵列之间的接口几乎不存在。 此外，由于在产生位线接触期间的氧化物塞和沉积在外围电路上的厚氧化物，可以解决常规问题。 在下板和硅晶片衬底之间沉积轻掺杂多晶硅以避免下板的电流泄漏。

公开(公告)号：US06168987A

公开(公告)日：2001-01-02

申请号：US08630013

申请日：1996-04-09

申请人： Erik S. Jeng ,  Ing-Ruey Liaw ,  Rong-Wu Chien

发明人： Erik S. Jeng ,  Ing-Ruey Liaw ,  Rong-Wu Chien

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10814 ,  H01L27/10885 ,  H01L28/91

摘要： The memory cell, such as a DRAM, has a crown-shaped capacitor structure and is formed on a substrate having a first conductivity type (i.e., p-type) and preferably has the following structure. Portions of the substrate are doped to have a conductivity type opposite that of the substrate (i.e, n-type) to form drain and source regions. A gate is formed between the drain and source regions having a gate oxide adjacent the substrate, a first polysilicon region (Poly-1), tungsten silicide layer, and an oxide layer and SiyNx, respectively, on the gate oxide. SiyNx spacers cover the sides of the gate regions. Above the oxide layer are tetetraethylorthosilicate (TEOS) and borophosphosilicate (BPSG) layers. A second polysilicon layer (Poly-2) is patterned to form a bitline which contacts the source region. A layer of tungsten silicide, oxide, and SiyNx are formed on top of the bitline. SiyNx spacers surround the bitline. A crown-shaped capacitor contacts the drain region. The crown-shaped capacitor comprises two polysilicon electrodes (Poly-3, Poly-4) separated by a thin dielectric layer. The inventive method fabricates the DRAM cell using only five masking steps. Thus, the process is more efficient than the prior art method for fabricating other DRAMS having crown-shaped capacitors. Also, the drain is exposed at the same time that the grid is formed using SiyNx spacers for etch self-alignment. This avoids precise masking or photolithography to expose this layer.

摘要翻译： 诸如DRAM的存储单元具有冠状电容器结构，并且形成在具有第一导电类型（即p型）的衬底上，并且优选具有以下结构。 衬底的一部分被掺杂以具有与衬底相反的导电类型（即n型），以形成漏极和源极区。 栅极形成在栅极氧化物附近具有栅极氧化物的漏极和源极区域之间，分别在栅极氧化物上的第一多晶硅区域（Poly-1），硅化钨层和氧化物层以及SiyNx。 SiyNx间隔物覆盖栅极区域的侧面。 在氧化物层上面是四乙基原硅酸盐（TEOS）和硼磷硅酸盐（BPSG）层。 将第二多晶硅层（Poly-2）图案化以形成接触源极区域的位线。 在位线的顶部形成硅化钨，氧化物和SiyNx层。 SiyNx间距围绕位线。 冠状电容器接触漏极区域。 冠形电容器包括由薄介电层分开的两个多晶硅电极（Poly-3，Poly-4）。 本发明的方法仅使用五个掩蔽步骤来制造DRAM单元。 因此，该方法比用于制造具有冠状电容器的其它DRAMS的现有技术方法更有效。 此外，漏极在与用于蚀刻自对准的SiyNx间隔物形成栅格的同时暴露。 这避免了精确的掩蔽或光刻曝光这一层。

公开(公告)号：US6103588A

公开(公告)日：2000-08-15

申请号：US122307

申请日：1998-07-24

申请人： Erik S. Jeng ,  Bi-Ling Chen ,  Hao-Chieh Liu

发明人： Erik S. Jeng ,  Bi-Ling Chen ,  Hao-Chieh Liu

IPC分类号： H01L21/60 ,  H01L21/20

CPC分类号： H01L21/76897

摘要： The present invention includes forming a first conductive layer on a semiconductor substrate, and forming a first dielectric layer on the first conductive layer. After patterning to etch the first dielectric layer and the first conductive layer, a second dielectric layer is formed on the semiconductor substrate and the first dielectric layer. Next, the second dielectric layer is anisotropically etched back to form a spacer on sidewalls of the first dielectric layer and the first conductive layer. A first silicon oxide layer is then formed over the semiconductor substrate, the first dielectric layer, and the spacer, followed by forming a photoresist layer on the first silicon oxide layer. A predetermined thickness of the first silicon oxide layer is removed by using the photoresist layer as a mask, and a polymer layer is then formed on the photoresist layer and the first silicon oxide layer. The polymer layer is anisotropically etched back to form a polymer spacer on sidewalls of the photoresist layer and the first silicon oxide layer. The first silicon oxide layer is then anisotropically etched back by using the polymer spacer as a mask to expose surface of the semiconductor substrate, wherein the spacer and the first dielectric layer are used for facilitating self-aligned etching. A second conductive layer is formed over the semiconductor substrate, surface of the second silicon oxide layer being exposed, and a second silicon oxide layer is formed over the second conductive layer and the first silicon oxide layer. Finally, a portion of the second silicon oxide layer is patterned to expose a portion of the second conductive layer, thereby forming the contact hole in the second oxide layer.

摘要翻译： 本发明包括在半导体衬底上形成第一导电层，并在第一导电层上形成第一电介质层。 在图案化以蚀刻第一介电层和第一导电层之后，在半导体衬底和第一介电层上形成第二电介质层。 接下来，将第二介电层各向异性地回蚀以在第一介电层和第一导电层的侧壁上形成间隔物。 然后在半导体衬底，第一介电层和间隔物上形成第一氧化硅层，随后在第一氧化硅层上形成光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模去除第一氧化硅层的预定厚度，然后在光致抗蚀剂层和第一氧化硅层上形成聚合物层。 聚合物层被各向异性地回蚀刻以在光致抗蚀剂层和第一氧化硅层的侧壁上形成聚合物间隔物。 然后通过使用聚合物间隔物作为掩模将第一氧化硅层各向异性地回蚀以暴露半导体衬底的表面，其中间隔物和第一介电层用于促进自对准蚀刻。 在半导体衬底上形成第二导电层，暴露第二氧化硅层的表面，在第二导电层和第一氧化硅层之上形成第二氧化硅层。 最后，将第二氧化硅层的一部分图案化以暴露第二导电层的一部分，从而在第二氧化物层中形成接触孔。

公开(公告)号：US5968711A

公开(公告)日：1999-10-19

申请号：US69376

申请日：1998-04-28

申请人： I-Ping Lee ,  Erik S. Jeng

发明人： I-Ping Lee ,  Erik S. Jeng

IPC分类号： H01L21/027 ,  H01L21/3213 ,  G03F7/36

CPC分类号： H01L21/32139 ,  H01L21/0276 ,  H01L21/32136

摘要： A new method of etching AlCu or AlSiCu lines is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A layer of AlCu or AlSiCu is deposited overlying insulating layer. A silicon nitride or titanium nitride/silicon dioxide layer is deposited overlying the metal layer wherein a hard mask is formed. The hard mask is covered with a layer of photoresist which is exposed to actinic light wherein the hard mask prevents reflection of the actinic light from its surface. The photoresist layer is developed and patterned to form the desired photoresist mask. The hard mask is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The AlCu or AlSiCu layer and the barrier layer not covered by the patterned hard mask are etched away to form metal lines having an outwardly tapered profile.

摘要翻译： 描述了蚀刻AlCu或AlSiCu线的新方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 半导体器件结构被绝缘层覆盖。 一层AlCu或AlSiCu沉积在绝缘层上。 在其上形成硬掩模的金属层上沉积氮化硅或氮化钛/二氧化硅层。 硬掩模被暴露于光化光的光致抗蚀剂层覆盖，其中硬掩模防止光化反射光从其表面。 显影和图案化光致抗蚀剂层以形成所需的光致抗蚀剂掩模。 硬掩模被蚀刻掉，其未被光致抗蚀剂掩模覆盖，留下图案化的硬掩模。 AlCu或AlSiCu层和未被图案化硬掩模覆盖的阻挡层被蚀刻掉以形成具有向外锥形轮廓的金属线。

公开(公告)号：US5952156A

公开(公告)日：1999-09-14

申请号：US893640

申请日：1997-07-11

申请人： Arthur Chin ,  Sen-Huan Huang ,  Erik S. Jeng

发明人： Arthur Chin ,  Sen-Huan Huang ,  Erik S. Jeng

IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  G03F7/00

CPC分类号： G03F7/09 ,  H01L21/0276 ,  H01L21/31144 ,  H01L21/76802

摘要： A method for forming for use within an integrated circuit a narrow aperture width patterned positive photoresist layer from a blanket positive photoresist layer. There is first formed over a semiconductor substrate a reflective layer. There is then formed upon the reflective layer a blanket positive photoresist layer. There is then photoexposed through a reticle the blanket positive photoresist layer to form a photoexposed blanket positive photoresist layer. Finally, the photoexposed blanket positive photoresist layer is developed to form a narrow aperture width patterned positive photoresist layer. The narrow aperture width patterned positive photoresist layer may then be employed as a narrow aperture width patterned positive photoresist etch mask layer in patterning a narrow aperture width patterned reflective layer from the reflective layer. In addition, at least the narrow aperture width patterned reflective layer may then be employed in forming an aperture at least partially through a substrate layer formed beneath the reflective layer. Typically, the aperture will be a contact or interconnection via completely through an insulator layer formed beneath the reflective layer. The method reduces the photoexposure energy and compensates for depth of focus limitations in forming the narrow aperture width patterned positive photoresist layer from the blanket positive photoresist layer.

摘要翻译： 一种用于在集成电路内使用来自覆盖正性光致抗蚀剂层的窄孔径宽度图案化正性光致抗蚀剂层的方法。 首先在半导体衬底上形成反射层。 然后在反射层上形成覆盖正的光致抗蚀剂层。 然后通过掩模版照射曝光的正性光致抗蚀剂层以形成光曝光的正性光致抗蚀剂层。 最后，将曝光的覆盖正性光致抗蚀剂层显影以形成窄孔径图案化正性光致抗蚀剂层。 然后可以将窄孔径宽度图案化的正性光致抗蚀剂层用作在从反射层图案化窄孔径宽度图案化反射层的窄孔径宽度图案化正性光致抗蚀剂蚀刻掩模层。 此外，至少可以将至少窄的孔径宽度图案化的反射层用于至少部分地穿过形成在反射层下面的衬底层形成孔。 通常，孔将是完全通过形成在反射层下面的绝缘体层的接触或互连。 该方法降低了光曝光能量，并且补偿了从积层正性光致抗蚀剂层形成窄孔径宽度图案化的正性光致抗蚀剂层的焦深限制。

公开(公告)号：US5834359A

公开(公告)日：1998-11-10

申请号：US924710

申请日：1997-08-29

申请人： Erik S. Jeng ,  Fu-Liang Yang

发明人： Erik S. Jeng ,  Fu-Liang Yang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/76229 ,  H01L21/76235 ,  Y10S148/05

摘要： A method for forming an isolation region in a semiconductor substrate is disclosed. The present invention includes forming an insulating layer on the semiconductor substrate, and then forming a dielectric layer on the insulating layer. After patterning to etch portions of the dielectric layer, the insulating layer and the semiconductor substrate are etched using the patterned dielectric layer as a mask, thereby forming a trench in the semiconductor substrate. Next, a first silicon oxide layer is formed over the semiconductor substrate, and the first silicon oxide layer is then anisotropically etched to form a spacer on the sidewalls of the trench. Thereafter, the semiconductor substrate is thermally oxidized to form a field oxide region over the semiconductor substrate, and a second silicon oxide layer is then formed over the field oxide region. Finally, the second silicon oxide layer is etched back until surface of the dielectric layer is exposed.

摘要翻译： 公开了一种在半导体衬底中形成隔离区域的方法。 本发明包括在半导体衬底上形成绝缘层，然后在绝缘层上形成电介质层。 在图案化以蚀刻介电层的部分之后，使用图案化的电介质层作为掩模来蚀刻绝缘层和半导体衬底，从而在半导体衬底中形成沟槽。 接下来，在半导体衬底上形成第一氧化硅层，然后对第一氧化硅层进行各向异性蚀刻，以在沟槽的侧壁上形成间隔物。 此后，半导体衬底被热氧化以在半导体衬底上形成场氧化物区域，然后在场氧化物区域上形成第二氧化硅层。 最后，第二氧化硅层被回蚀，直到电介质层的表面露出。

公开(公告)号：US07473599B2

公开(公告)日：2009-01-06

申请号：US11655712

申请日：2007-01-18

申请人： Erik S. Jeng

发明人： Erik S. Jeng

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  G11C16/0475 ,  H01L29/66833 ,  H01L29/7923

摘要： A method for manufacturing a memory unit capable of storing multibits binary information. A gate is formed on a dielectric layer over a semiconductor substrate. Next, a first etching is performed to etch the semiconductor substrate by using the gate acting as an etching mask to remove exposed surface of the dielectric layer. Subsequently, a first oxide layer is conformally formed on the gate and the semiconductor substrate. An charge-trapping layer is conformally formed on the first oxide layer, and subsequently a second oxide layer is conformally formed on the isolating layer. Next, a second etching is performed to etch the second oxide layer and the charging-trapping layer to form sandwich spacers composed of the second oxide layer/the isolating layer/the first oxide layer on the substrate and the gate sidewall. An ion implantation is performed by using the gate and the spacers acting as a mask to form source/drain doped regions in the semiconductor substrate, wherein junctions of the substrate to the source/drain doped regions locate right under the spacers.

摘要翻译： 一种用于制造能够存储多位二进制信息的存储单元的方法。 在半导体衬底上的电介质层上形成栅极。 接下来，通过使用用作蚀刻掩模的栅极来蚀刻半导体衬底以去除电介质层的暴露表面，进行第一蚀刻。 随后，在栅极和半导体衬底上共形形成第一氧化物层。 在第一氧化物层上保形地形成电荷捕获层，随后在隔离层上保形地形成第二氧化物层。 接下来，进行第二蚀刻以蚀刻第二氧化物层和充电捕获层，以形成由衬底上的第二氧化物层/隔离层/第一氧化物层和栅极侧壁构成的夹层隔板。 通过使用栅极和间隔物作为掩模来进行离子注入，以在半导体衬底中形成源极/漏极掺杂区域，其中衬底与源极/漏极掺杂区域的接合位于间隔物的正下方。

公开(公告)号：US07375394B2

公开(公告)日：2008-05-20

申请号：US11175417

申请日：2005-07-06

申请人： Erik S. Jeng

发明人： Erik S. Jeng

IPC分类号： H01L29/792

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/785 ,  Y10S257/90

摘要： The present invention includes a semiconductor layer formed over an insulation layer and a substrate. Doped regions are formed in a portion of the semiconductor layer. A gate dielectric and a gate are respectively formed over the semiconductor layer. The arrangement of the gate sidewall and semiconductor layer surface is substantially orthogonal, multi-portion dielectric layer is formed on the gate and a portion of the silicon layer. Charge trapping dielectrics are attached on the multi-portion dielectric layer acting as carrier trapping structure. The gate-to-source/drain non-overlapped implantation is capable of storing multi-bits per transistor.

摘要翻译： 本发明包括在绝缘层和基板上形成的半导体层。 掺杂区域形成在半导体层的一部分中。 在半导体层上分别形成栅极电介质和栅极。 栅极侧壁和半导体层表面的布置基本正交，在栅极和硅层的一部分上形成多部分电介质层。 电荷捕获电介质附着在作为载流子俘获结构的多部分电介质层上。 栅极到源极/漏极非重叠注入能够存储每个晶体管的多位。