公开(公告)号：US6071789A

公开(公告)日：2000-06-06

申请号：US190054

申请日：1998-11-10

申请人： Fu-Liang Yang ,  Erik S. Jeng ,  Bih-Tiao Lin ,  I-Ping Lee

发明人： Fu-Liang Yang ,  Erik S. Jeng ,  Bih-Tiao Lin ,  I-Ping Lee

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10894 ,  H01L28/60 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10897 ,  H01L28/55

摘要： A method for simultaneously forming a storage node and a plurality of interconnection in fabricating a semiconductor device on a substrate. The method comprises the steps of: forming a first dielectric layer over said cell array area and said periphery; forming a plurality of first contact holes through said first dielectric layer in said cell array area and said periphery area, said periphery area including a bitline and a word line, said word line and said bitline being used for addressing said memory cell; forming a first conductive layer in said plurality of first contact holes and on said first dielectric layer; patterning and etching said first conductive layer to form said storage node and said plurality of interconnections simultaneously; forming a second dielectric layer and a second conductive layer subsequently on said first dielectric layer, said storage node and said plurality of interconnections; and patterning and etching said second dielectric layer and said second conductive layer to form a charge storage means and a plurality of contact plugs.

摘要翻译： 一种用于在衬底上制造半导体器件的同时形成存储节点和多个互连的方法。 该方法包括以下步骤：在所述单元阵列区域和所述周边上形成第一介电层; 通过所述单元阵列区域和所述外围区域中的所述第一介电层形成多个第一接触孔，所述外围区域包括位线和字线，所述字线和所述位线用于寻址所述存储单元; 在所述多个第一接触孔和所述第一介电层上形成第一导电层; 图案化和蚀刻所述第一导电层以同时形成所述存储节点和所述多个互连; 随后在所述第一介电层，所述存储节点和所述多个互连上形成第二电介质层和第二导电层; 以及图案化和蚀刻所述第二介电层和所述第二导电层以形成电荷存储装置和多个接触插塞。

公开(公告)号：US6060348A

公开(公告)日：2000-05-09

申请号：US184341

申请日：1998-11-02

申请人： Fu-Liang Yang ,  Wei-Ray Lin ,  Ming-Hong Kuo ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Wei-Ray Lin ,  Ming-Hong Kuo ,  Erik S. Jeng

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/76224

摘要： A method for forming planarized isolation by combining LOCOS and STI isolation processes is described. A first nitride layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. The first nitride layer and pad oxide layer are etched through where they are not covered by a mask to provide openings where the surface of the semiconductor substrate is exposed wherein there is at least one wide opening and one narrow opening. A second nitride layer is deposited over the substrate and etched back to leave spacers on the sidewalls of the openings wherein the narrow opening is filled by the spacers. The exposed semiconductor substrate within the wide opening is oxidized wherein a field oxide region is formed within the wide opening. A portion of the first nitride layer and spacers is etched away whereby the semiconductor substrate within the narrow opening is exposed. A trench is etched into the semiconductor substrate where it is exposed within the narrow opening. An oxide layer is deposited overlying the first nitride layer and field oxide region and filling the trench wherein the oxide layer filling the trench forms a shallow trench isolation region. The oxide layer is polished away with a polish stop at the first nitride layer. The first nitride layer, the spacers, and the pad oxide layer are removed, completing formation of both a field oxide region and a shallow trench isolation region in the fabrication of an integrated circuit device.

摘要翻译： 描述了通过组合LOCOS和STI隔离过程形成平坦化隔离的方法。 在半导体衬底的表面上的衬垫氧化物层上沉积第一氮化物层。 蚀刻第一氮化物层和焊盘氧化物层，其中它们未被掩模覆盖，以提供其中存在至少一个宽开口和一个窄开口的半导体衬底的表面的开口。 第二氮化物层沉积在衬底上并被回蚀刻以在开口的侧壁上留下间隔物，其中窄的开口被间隔物填充。 在宽开口内的暴露的半导体衬底被氧化，其中在宽开口内形成场氧化物区域。 第一氮化物层和间隔物的一部分被蚀刻掉，由此暴露窄开口内的半导体衬底。 沟槽被蚀刻到半导体衬底中，其中它暴露在窄的开口内。 沉积覆盖在第一氮化物层和场氧化物区域上并填充沟槽的氧化物层，其中填充沟槽的氧化物层形成浅沟槽隔离区域。 在第一氮化物层处用抛光停止层抛光氧化物层。 去除第一氮化物层，间隔物和衬垫氧化物层，在集成电路器件的制造中完成场氧化物区域和浅沟槽隔离区域的形成。

公开(公告)号：US5956594A

公开(公告)日：1999-09-21

申请号：US184345

申请日：1998-11-02

申请人： Fu-Liang Yang ,  Bi-Ling Chen ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Bi-Ling Chen ,  Erik S. Jeng

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L28/60 ,  H01L27/10852 ,  H01L27/10888

摘要： A method for creating a DRAM device, featuring the simultaneous formation of a capacitor plate, used for a stacked capacitor structure, and the formation of a metal contact structure, and of a word line contact structure, has been developed. The process features the deposition of a barrier layer, and an overlying tungsten layer, on a storage node electrode, and with the deposition also completely filling a metal contact hole, and a word line hole. A patterning procedure, using an anisotropic RIE procedure, removes unwanted regions of tungsten and barrier layer, resulting in a capacitor plate, a metal contact structure, and a word line structure, all comprised of tungsten and the barrier layers, and all formed via one deposition procedure, and patterned using one RIE procedure.

摘要翻译： 已经开发了用于产生用于层叠电容器结构的电容器板的同时形成以及金属接触结构的形成以及字线接触结构的DRAM器件的制造方法。 该方法的特征在于在存储节点电极上沉积阻挡层和覆盖的钨层，并且沉积也完全填充金属接触孔和字线孔。 使用各向异性RIE程序的图案化步骤去除钨和阻挡层的不需要的区域，导致电容器板，金属接触结构和字线结构，全部由钨和阻挡层组成，并且都通过一个 沉积程序，并使用一个RIE程序进行图案化。

公开(公告)号：US5804852A

公开(公告)日：1998-09-08

申请号：US876914

申请日：1997-06-16

申请人： Fu-Liang Yang ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Erik S. Jeng

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A multiple crown shaped polysilicon structure, used for a lower electrode of a DRAM stacked capacitor structure, has been developed. The multiple crown shaped, lower electrode, is formed overlying, and contacting a polysilicon fill layer, that is located between insulator encapsulated polycide gate structures. The polysilicon fill layer, in turn, contacts an underlying source/drain region of a transfer gate transistor. The multiple crown shaped lower electrode is comprised vertical polysilicon shapes, connected to an underlying, horizontal polysilicon shape, with the horizontal polysilicon shape overlying the polysilicon fill layer. One to three, vertical polysilicon shapes, are used on each side of the multiple crown shaped lower electrode.

摘要翻译： 已经开发了用于DRAM堆叠电容器结构的下电极的多冠状多晶硅结构。 形成多个冠状的下电极，其位于绝缘体封装的多晶硅栅极结构之间，覆盖并接触多晶硅填充层。 多晶硅填充层又接触传输栅晶体管的底层源/漏区。 多冠状下电极包括垂直多晶硅形状，连接到下面的水平多晶硅形状，其中水平多晶硅形状覆盖多晶硅填充层。 在多冠状下电极的每一侧使用一至三个垂直多晶硅形状。

公开(公告)号：US5804489A

公开(公告)日：1998-09-08

申请号：US679196

申请日：1996-07-12

申请人： Fu-Liang Yang ,  Erik S. Jeng ,  Yu-Chun Ho ,  Bin Liu ,  Chao-Ming Koh

发明人： Fu-Liang Yang ,  Erik S. Jeng ,  Yu-Chun Ho ,  Bin Liu ,  Chao-Ming Koh

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The present invention is a method of manufacturing crown shape capacitors in the semiconducter memories. Using a single step etching to farbricate the capacitor in a DRAM cell. The method can form side wall polymers and etching byproductions on the surface of the first polysilicon, using the side wall polymers and the etching byproductions as a mask to form the crown shape capacitors with pillars. Moreover, this present invention can form the crown shape structure and pillars in the same step, the crown shape structure and the pillars increase the surface area of the capacitor. Therefore the present invention will increase the performance of the capacitor.

摘要翻译： 本发明是在半导体存储器中制造冠状电容器的方法。 使用单步蚀刻来超越DRAM单元中的电容器。 该方法可以使用侧壁聚合物和蚀刻副产物作为掩模形成侧壁聚合物并在第一多晶硅的表面上蚀刻副产物，以形成具有支柱的冠状电容器。 此外，本发明可以在相同的步骤中形成冠状结构和柱，冠状结构和柱增加电容器的表面积。 因此，本发明将增加电容器的性能。

公开(公告)号：US5792689A

公开(公告)日：1998-08-11

申请号：US827817

申请日：1997-04-11

申请人： Fu-Liang Yang ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Erik S. Jeng

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method is described using a single photoresist mask to make a double-crown-shaped DRAM capacitor self-aligned to the capacitor node contact. After forming the DRAM FETs and the bit lines, a planar BPSG layer, a first polysilicon layer, and a CVD oxide layer are deposited. A node contact photoresist mask is used to form first openings in the CVD oxide in which silicon nitride sidewall spacers are formed. A smaller second opening is etched in the first opening to form node contact openings to the DRAM FET source/drain areas. A conformal second polysilicon layer is deposited to form node contacts in the second openings and over the free-standing sidewall spacers. A planar spin-on glass layer is then used as a self-aligned mask to etch back to expose the second polysilicon layer, which is then removed from the top of the sidewall spacers. After removing the spin-on glass an anisotropic etch is used to form the double-crown-shaped capacitor bottom electrodes self-aligned to the node contacts. The bottom electrode surface is roughened to increase the capacitance area, and the sidewall spacers are removed. An interelectrode dielectric layer and a third polysilicon layer are used to complete the double-crown-shaped stacked capacitors.

摘要翻译： 使用单个光致抗蚀剂掩模描述一种方法，以使双冠形DRAM电容器与电容器节点接触自对准。 在形成DRAM FET和位线之后，沉积平面BPSG层，第一多晶硅层和CVD氧化物层。 使用节点接触光刻胶掩模在其中形成氮化硅侧壁间隔物的CVD氧化物中形成第一开口。 在第一开口中蚀刻较小的第二开口以形成到DRAM FET源极/漏极区域的节点接触开口。 沉积保形第二多晶硅层以在第二开口中并且在独立的侧壁间隔物上形成节点接触。 然后将平面旋涂玻璃层用作自对准掩模以回蚀以暴露第二多晶硅层，然后从侧壁间隔物的顶部除去第二多晶硅层。 在去除旋涂玻璃之后，使用各向异性蚀刻来形成与节点接触自对准的双冠状电容器底部电极。 底部电极表面被粗糙化以增加电容面积，并且去除侧壁间隔物。 使用电极间电介质层和第三多晶硅层来完成双冠形叠层电容器。

公开(公告)号：US06278189B1

公开(公告)日：2001-08-21

申请号：US09428571

申请日：1999-10-28

申请人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

发明人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

IPC分类号： H01L2348

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.

摘要翻译： 公开了一种在高密度集成电路中制造接触孔的方法及其结构。 显示出通过明智地整合形成浅锥形孔的过程与自对准技术，可以以减少数量的掩模处理步骤来制造自对准的孔。 这是通过首先通过各向同性蚀刻在衬底中的某些区域上形成一定深度的浅锥形孔，然后通过各向异性蚀刻将它们扩展到对应于它们允许接触的区域的全深度来实现的。 最终的结果是整套孔是自对准的并且通过单个光致抗蚀剂掩模形成。

公开(公告)号：US5994228A

公开(公告)日：1999-11-30

申请号：US827818

申请日：1997-04-11

申请人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

发明人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L21/00 ,  H01L21/70

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002

摘要： A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.

摘要翻译： 公开了一种在高密度集成电路中制造接触孔的方法及其结构。 显示出通过明智地整合形成浅锥形孔的过程与自对准技术，可以以减少数量的掩模处理步骤来制造自对准的孔。 这是通过首先通过各向同性蚀刻在衬底中的某些区域上形成一定深度的浅锥形孔，然后通过各向异性蚀刻将它们扩展到对应于它们允许接触的区域的全深度来实现的。 最终的结果是整套孔是自对准的并且通过单个光致抗蚀剂掩模形成。

公开(公告)号：US5834359A

公开(公告)日：1998-11-10

申请号：US924710

申请日：1997-08-29

申请人： Erik S. Jeng ,  Fu-Liang Yang

发明人： Erik S. Jeng ,  Fu-Liang Yang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/76229 ,  H01L21/76235 ,  Y10S148/05

摘要： A method for forming an isolation region in a semiconductor substrate is disclosed. The present invention includes forming an insulating layer on the semiconductor substrate, and then forming a dielectric layer on the insulating layer. After patterning to etch portions of the dielectric layer, the insulating layer and the semiconductor substrate are etched using the patterned dielectric layer as a mask, thereby forming a trench in the semiconductor substrate. Next, a first silicon oxide layer is formed over the semiconductor substrate, and the first silicon oxide layer is then anisotropically etched to form a spacer on the sidewalls of the trench. Thereafter, the semiconductor substrate is thermally oxidized to form a field oxide region over the semiconductor substrate, and a second silicon oxide layer is then formed over the field oxide region. Finally, the second silicon oxide layer is etched back until surface of the dielectric layer is exposed.

摘要翻译： 公开了一种在半导体衬底中形成隔离区域的方法。 本发明包括在半导体衬底上形成绝缘层，然后在绝缘层上形成电介质层。 在图案化以蚀刻介电层的部分之后，使用图案化的电介质层作为掩模来蚀刻绝缘层和半导体衬底，从而在半导体衬底中形成沟槽。 接下来，在半导体衬底上形成第一氧化硅层，然后对第一氧化硅层进行各向异性蚀刻，以在沟槽的侧壁上形成间隔物。 此后，半导体衬底被热氧化以在半导体衬底上形成场氧化物区域，然后在场氧化物区域上形成第二氧化硅层。 最后，第二氧化硅层被回蚀，直到电介质层的表面露出。

公开(公告)号：US5677227A

公开(公告)日：1997-10-14

申请号：US709898

申请日：1996-09-09

申请人： Fu-Liang Yang ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Erik S. Jeng

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A process for creating a stacked capacitor, dynamic random access memory device, featuring increased capacitor surface area, resulting from a polysilicon, triple crown shaped, lower electrode structure, and also featuring self-alignment of the stacked capacitor contact structure, to a bit line contact structure, has been developed. The triple crown shaped, lower electrode structure is comprised of polysilicon spacers, formed via use of polysilicon and silicon oxide, low pressure chemical deposition, and anisotropic RIE, procedures.

摘要翻译： 一种用于制造堆叠电容器的过程，动态随机存取存储器件，其特征在于由多晶硅，三冠形，下电极结构以及叠层电容器接触结构的自对准引起的电容器表面积增加到位线 接触结构，已经开发。 三冠形的下电极结构由通过使用多晶硅和氧化硅形成的多晶硅间隔物，低压化学沉积和各向异性RIE程序组成。