公开(公告)号：US09685541B2

公开(公告)日：2017-06-20

申请号：US15247909

申请日：2016-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhen-Cyuan Li ,  Shui-Yen Lu ,  Yen-Liang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/31116 ,  H01L29/6656 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate, having a fin structure disposed thereon, a gate structure, crossing over parts of the fin structure. The top surface of the fin structure which is covered by the gate structure is defined as a first top surface, and the top surface of the fin structure which is not covered by the gate structure is defined as a second top surface. The first top surface is higher than the second top surface, and a spacer covers the sidewalls of the gate structure. The spacer includes an inner spacer and an outer spacer, and the outer pacer further contacts the second top surface of the fin structure directly.

公开(公告)号：US09627541B2

公开(公告)日：2017-04-18

申请号：US14741464

申请日：2015-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhen-Cyuan Li ,  Nan-Yuan Huang ,  Shui-Yen Lu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851

Abstract: A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The spacer structure is disposed on a sidewall of the gate structure. The spacer structure includes a first spacer with a first height and a second spacer with a second height, wherein the first spacer is disposed between the second spacer, and the first height is different from the second height. The source/drain region is disposed in a semiconductor layer at two sides of the spacer structure. The present invention further provides a method of forming the same.

公开(公告)号：US20170084688A1

公开(公告)日：2017-03-23

申请号：US14884787

申请日：2015-10-16

Applicant: United Microelectronics Corp.

Inventor： Jhen-Cyuan Li ,  Nan-Yuan Huang ,  Shui-Yen Lu

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L21/76232 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate, having a recess disposed therein, an insulating layer filled in the recess and disposed on a surface of the substrate, and at least one fin structure disposed in the insulating layer, the fin structure consisting of two terminal parts and a central part disposed between two terminal parts. The terminal parts are disposed on the surface of the substrate and directly contact the substrate, and the central part is disposed right above the recess.

公开(公告)号：US20160365431A1

公开(公告)日：2016-12-15

申请号：US15247909

申请日：2016-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhen-Cyuan Li ,  Shui-Yen Lu ,  Yen-Liang Wu

IPC: H01L29/66 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/31116 ,  H01L29/6656 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate, having a fin structure disposed thereon, a gate structure, crossing over parts of the fin structure. The top surface of the fin structure which is covered by the gate structure is defined as a first top surface, and the top surface of the fin structure which is not covered by the gate structure is defined as a second top surface. The first top surface is higher than the second top surface, and a spacer covers the sidewalls of the gate structure. The spacer includes an inner spacer and an outer spacer, and the outer pacer further contacts the second top surface of the fin structure directly.

Abstract translation: 本发明提供一种半导体结构，其包括具有设置在其上的翅片结构的基板，栅极结构，跨越鳍片结构的一部分。 由栅极结构覆盖的翅片结构的上表面被定义为第一顶表面，并且未被栅极结构覆盖的翅片结构的顶表面被定义为第二顶表面。 第一顶表面高于第二顶表面，间隔件覆盖栅结构的侧壁。 间隔件包括内隔离件和外间隔件，并且外起重器还直接接触翅片结构的第二顶表面。

公开(公告)号：US20160118481A1

公开(公告)日：2016-04-28

申请号：US14556690

申请日：2014-12-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhen-Cyuan Li ,  Shui-Yen Lu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28017 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device comprises a substrate, a gate structure and a gate spacer. The substrate has a semiconductor fin protruding from a surface of the substrate. The gate structure is disposed on the semiconductor fin. The gate spacer is disposed on sidewalls of the gate structure, wherein the gate spacer comprises a first material layer and a second material layer stacked with each other and both of these two material layers are directly in contact with the gate structure.

Abstract translation: 半导体器件包括衬底，栅极结构和栅极间隔物。 衬底具有从衬底的表面突出的半导体鳍片。 栅极结构设置在半导体鳍片上。 栅极间隔物设置在栅极结构的侧壁上，其中栅极间隔物包括彼此堆叠的第一材料层和第二材料层，并且这两个材料层都直接与栅极结构接触。

公开(公告)号：US20160104627A1

公开(公告)日：2016-04-14

申请号：US14533105

申请日：2014-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhen-Cyuan Li ,  Shui-Yen Lu

IPC: H01L21/308 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/3081 ,  H01L21/02057 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31116 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a cap layer on the fin-shaped structure; removing part of the cap layer on top of the fin-shaped structure; removing part of the fin-shaped structure; removing the remaining cap layer; and removing part of the remaining fin-shaped structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成翅片状结构; 在鳍状结构上形成盖层; 去除所述鳍状结构顶部上的所述盖层的一部分; 去除鳍状结构的一部分; 去除剩余的盖层; 并且去除剩余的鳍状结构的一部分。

公开(公告)号：US09305847B2

公开(公告)日：2016-04-05

申请号：US14314425

申请日：2014-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Chi-Mao Hsu ,  Yuan-Chi Pai ,  Yu-Hong Kuo ,  Nien-Ting Ho

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

CPC classification number: H01L21/82385 ,  H01L21/28026 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括以下步骤。 形成包括具有第一导电类型的第一晶体管，具有第二导电类型的第二晶体管和具有第一导电类型的第三晶体管的衬底。 内层电介质层形成在衬底上，并且包括对应于第一晶体管的第一栅极沟槽，对应于第二晶体管的第二栅极沟槽和对应于第三晶体管的第三栅极沟槽。 在内层电介质层上形成功函数金属层。 在功函数金属层上涂布抗反射层。 去除第二晶体管上的抗反射层和第三栅极沟槽的顶部以暴露功函数金属层。 暴露的功能金属层被去除。

公开(公告)号：US20160005866A1

公开(公告)日：2016-01-07

申请号：US14509449

申请日：2014-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Liang Wu ,  Yu-Cheng Tung ,  Jhen-Cyuan Li ,  Shui-Yen Lu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7848

Abstract: A fin field effect transistor (FinFET) with improved electrical performance and a method of manufacturing the same are disclosed. A FinFET comprises a substrate having a top surface and an insulation. At least a recessed fin is extended upwardly from the top surface of the substrate, and at least a gate stack formed above the substrate, wherein the gate stack is extended perpendicularly to an extending direction of the recessed fin, and the recessed fin is outside the gate stack. The insulation comprises a lateral portion adjacent to the recessed fin, and a central portion contiguous to the lateral portion, wherein a top surface of the lateral portion is higher than a top surface of the central portion. A top surface of the recessed fin is lower than the top surface of the central portion of the insulation.

Abstract translation: 公开了具有改进的电气性能的鳍式场效应晶体管（FinFET）及其制造方法。 FinFET包括具有顶表面和绝缘体的衬底。 至少一个凹入的翅片从衬底的顶表面向上延伸，并且至少形成在衬底上方的栅堆叠，其中栅叠层垂直于凹鳍的延伸方向延伸，并且凹鳍位于 门堆叠 所述绝缘体包括与所述凹形翅片相邻的侧面部分和与所述侧面部分邻接的中心部分，其中所述侧部分的顶表面高于所述中心部分的顶表面。 凹陷翅片的顶面低于绝缘体中心部分的顶面。

公开(公告)号：US20150126015A1

公开(公告)日：2015-05-07

申请号：US14583122

申请日：2014-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

IPC: H01L49/02

CPC classification number: H01L28/20 ,  H01L21/76897 ,  H01L27/0629 ,  H01L28/24 ,  H01L29/66545

Abstract: A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.

Abstract translation: 半导体结构包括基板，抗蚀剂层，电介质材料，两个U形金属层和两种金属。 衬底具有隔离结构。 抗蚀剂层位于隔离结构上。 介电材料位于抗蚀剂层上。 两个U形金属层位于电介质材料的两侧和抗蚀剂层上。 两个金属分别位于两个U形金属层上。 以这种方式提供了用于形成所述半导体结构的半导体工艺。

公开(公告)号：US20150064861A1

公开(公告)日：2015-03-05

申请号：US14016393

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Yuan-Chi Pai ,  Fong-Lung Chuang

IPC: H01L29/66

CPC classification number: H01L29/66484 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.

Abstract translation: 提供一种制造半导体器件的方法。 提供了分别形成在第一区域和第二区域中的具有第一栅极和第二栅极的衬底。 在衬底上形成底层以覆盖第一区域中的第一栅极和第二区域中的第二栅极。 在第一区域中的底层上形成具有预定厚度的图案化掩模。 通过图案化掩模去除对应于第二区域中的第二栅极的底层以暴露第二栅极，其中对应于第一区域中的第一栅极的底层被部分消耗以暴露第一栅极的部分。