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公开(公告)号：US08560989B2
公开(公告)日：2013-10-15
申请号：US13311832
申请日：2011-12-06
申请人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Michael H. Wood , Vladimir Zolotov
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Michael H. Wood , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/10 , G06F2217/62
摘要： Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.
摘要翻译： 将集成电路设计的统计时钟周期计算和闭合时序的系统和方法设计到最大时钟周期或周期。 该方法包括将用于集成电路或集成电路的区域的至少一个电路路径的设计和定时模型加载到计算设备中。 该方法还包括使用加载的设计和定时模型来执行至少一个电路路径的统计静态时序分析（SSTA），以获得松散的规范数据。 该方法还包括基于从SSTA获得的松弛规范数据，以线性规范形式计算集成电路或集成电路的指定区域的最大电路时钟周期。
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42.发明授权Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence 失效用于执行集成电路的参数化统计静态时序分析（SSTA）的方法，系统和程序存储装置，其考虑到建立和保持边际相互依赖性公开(公告)号：US08468483B2
公开(公告)日：2013-06-18
申请号：US13279373
申请日：2011-10-24
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimir Zolotov
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimir Zolotov
IPC分类号： G06F9/455
CPC分类号： G06F17/5031 , G06F2217/84
摘要： In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree.
摘要翻译： 在统计静态时序分析（SSTA）方法，系统和程序存储装置的实施例中，需要检查的电路块（例如，锁存器，触发器等）的建立时间和保持时间裕度之间的相互依赖关系 确定设置和保持时序约束），同时考虑到多个参数的可能变化（例如，使用变异感知特性技术）。 执行结合电路块的电路的参数化统计静态时序分析（SSTA），以便以统计参数化形式确定电路块的建立和保持时间。 基于设置和保持时间间隔之间的相互依赖性，可以以统计参数化形式确定建立和保持时间约束。 最后，可以根据建立和保持时间约束来检查SSTA期间确定的建立和保持时间，以确定是否违反时间限制，以及在何种程度上。
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43.发明授权Methods for statistical slew propagation during block-based statistical static timing analysis 有权基于块统计静态时序分析的统计转换传播方法公开(公告)号：US08086976B2
公开(公告)日：2011-12-27
申请号：US12121023
申请日：2008-05-15
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Methods for statistical slew propagation in static statistical timing analysis. The method includes projecting a canonical approximation of an input slew over a timing path to a first corner and using the projected input slew to calculate a delay and an output slew at the first corner. The method further includes perturbing the canonical approximation of the input slew to a different corner, calculating a delay and an output slew at the different corner using the perturbed input slew canonical, and determining a sensitivity of the delay and the output slew to a plurality of parameters, simultaneous with implicit sensitivity calculations to the input slew, with finite difference calculations between the first corner and perturbed data.
摘要翻译： 静态统计时序分析中统计转换传播的方法。 该方法包括将定时路径上的输入转换的规范近似投影到第一角，并且使用投影输入转换来计算在第一角处的延迟和输出。 该方法进一步包括将输入转换的规范近似扰乱到不同的角，使用干扰的输入转换来计算延迟和在不同角上的输出转换，并且将延迟和输出转换的灵敏度确定为多个 参数，同时与隐式灵敏度计算到输入转换，在第一个角和扰动数据之间进行有限差分计算。
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44.发明授权System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis 有权用于在统计静态时序分析中调节非高斯和非线性变化源的系统和方法公开(公告)号：US08015525B2
公开(公告)日：2011-09-06
申请号：US12114203
申请日：2008-05-02
CPC分类号： G06F17/5031
摘要： There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.
摘要翻译： 提供了一种用于具有两个或多个数字元件的电路的统计时序分析和优化的系统和方法。 该系统包括至少一个参数输入和统计静态时序分析器和电路优化器。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器和电路优化器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个，并且用于修改电路的组件尺寸以改变门时序特性 基于信号到达时间和信号所需时间中的至少一个。
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公开(公告)号：US20110106497A1
公开(公告)日：2011-05-05
申请号：US12610291
申请日：2009-10-31
IPC分类号： G21C17/00
CPC分类号： G06F17/5045 , G06F2217/10 , G06F2217/82
摘要： Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme. It is then determined whether the parametric chip yield computed is optimal. If the parametric chip yield is not optimal, the voltage binning scheme is altered and the compute and determine steps are repeated. Otherwise the binning scheme is left unaltered.
摘要翻译： 提供了用于提高制造芯片的参数芯片产量的技术。 在一个方面，提供了一种用于优化参数芯片产量的方法。 该方法包括以下步骤。 基于经受给定电压合并方案的多个制造的芯片的性能和功耗来计算参数芯片产量。 然后确定计算的参数芯片产量是否是最佳的。 如果参数芯片产量不是最优的，则改变电压组合方案，并重复计算和确定步骤。 否则，binning方案保持不变。
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46.发明授权Method and apparatus for incrementally computing criticality and yield gradient 有权递增计算临界和屈服梯度的方法和装置公开(公告)号：US07861199B2
公开(公告)日：2010-12-28
申请号：US11870672
申请日：2007-10-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031
摘要： In one embodiment, the invention is a method and apparatus for incrementally computing criticality and yield gradient. One embodiment of a method for computing a diagnostic metric for a circuit includes modeling the circuit as a timing graph, determining a chip slack for the circuit, determining a slack of at least one diagnostic entity, and computing a diagnostic metric relating to the diagnostic entity(ies) from the chip slack and the slack of the diagnostic entity(ies).
摘要翻译： 在一个实施例中，本发明是用于递增地计算临界度和屈服梯度的方法和装置。 用于计算电路的诊断度量的方法的一个实施例包括将电路建模为定时图，确定电路的芯片松弛，确定至少一个诊断实体的松弛，以及计算与诊断实体有关的诊断度量 （ies）从芯片松弛和诊断实体的松弛。
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公开(公告)号：US07849429B2
公开(公告)日：2010-12-07
申请号：US12053887
申请日：2008-03-24
CPC分类号： G06F17/5031
摘要： A method is provided for memory conservation in statistical static timing analysis. A timing graph is created with a timing run in a statistical static timing analysis program. A plurality of nodes in the timing graph that are candidates for a partial store and constraint points are identified. Timing data is persistently stored at constraint points. The persistent timing data is retrieved from the constraint points and used to calculate intermediate timing data at the plurality of nodes during timing analysis.
摘要翻译： 在统计静态时序分析中提供了一种用于存储器保存的方法。 在统计静态时序分析程序中使用时序运行创建时序图。 识别作为部分存储和约束点的候选的定时图中的多个节点。 定时数据被持久存储在约束点。 从约束点检索持续定时数据，并用于在定时分析期间计算多个节点处的中间定时数据。
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48.发明申请METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING 有权用于产生用于速度测试的测试模式的方法和装置公开(公告)号：US20100287432A1
公开(公告)日：2010-11-11
申请号：US12464025
申请日：2009-05-11
IPC分类号： G01R31/28
CPC分类号： G01R31/318328 , G01R31/318342
摘要： In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.
摘要翻译： 在一个实施例中，本发明是产生用于在速测试中的测试图案的方法和装置。 由通用计算设备使用的方法的一个实施例被配置为生成用于测试集成电路芯片的一组测试图案，包括由通用计算设备的输入设备接收与 所述集成电路芯片和所述集成电路芯片的逻辑电路，并且由所述通用计算设备的处理器根据所述统计定时信息生成所述一组测试图案，同时选择一组在其上测试的路径 一套测试模式。
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49.发明申请Method of Performing Timing Analysis on Integrated Circuit Chips with Consideration of Process Variations 有权对考虑过程变化的集成电路芯片执行时序分析的方法公开(公告)号：US20100180243A1
公开(公告)日：2010-07-15
申请号：US12354306
申请日：2009-01-15
申请人： Debjit Sinha , Eric A. Foreman , Peter A. Habitz , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Debjit Sinha , Eric A. Foreman , Peter A. Habitz , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for verifying whether a circuit meets timing constraints by performing an incremental static timing analysis in which slack is represented by a distribution that includes sensitivities to various process variables. The slack at an endpoint is computed by propagating the arrival times and required arrival times of paths leading up to the endpoint. The computation of arrival and required arrival times needs the computation of delays of individual gate and wire segments in each path that leads to the endpoint. The mixed mode adds a deterministic timing to the statistical timing (DSTA+SSTA).
摘要翻译： 一种用于通过执行增量静态时序分析来验证电路是否满足时序约束的方法，其中松弛由包括对各种过程变量的灵敏度的分布表示。 通过传播到达端点的路径的到达时间和所需到达时间来计算端点的松弛度。 到达和到达时间的计算需要计算通向端点的每个路径中各个门和线段的延迟。 混合模式为统计时间（DSTA + SSTA）增加了一个确定性时序。
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50.发明申请公开(公告)号：US20090271751A1
公开(公告)日：2009-10-29
申请号：US12111634
申请日：2008-04-29
IPC分类号： G06F17/50
CPC分类号： G01R31/318371
摘要： In one embodiment, the invention is a method and apparatus for statistical path selection for at-speed testing. One embodiment of a method for selecting a path of an integrated circuit chip for at-speed testing includes computing a process coverage metric for a plurality of paths in the integrated circuit chip and selecting at least one path that maximizes the process coverage metric.
摘要翻译： 在一个实施例中，本发明是用于速度测试的统计路径选择的方法和装置。 用于选择用于高速测试的集成电路芯片的路径的方法的一个实施例包括计算集成电路芯片中的多个路径的处理覆盖度量度，并且选择使过程覆盖度量最大化的至少一个路径。
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