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公开(公告)号：US20210272634A1
公开(公告)日：2021-09-02
申请号：US17179409
申请日：2021-02-19
Applicant: Winbond Electronics Corp.
Inventor： Riichiro Shirota , Masaru Yano
Abstract: A semiconductor memory device capable of reducing failure caused by a source side effect after a large number of W/E cycles is provided. A reading method of a NAND flash memory includes: dividing multiple word lines connected to each memory cell of a NAND string into a group 1 of word lines WL0 to WLi−1, a group 2 of word lines WLi to WLj, . . . , a group y of word lines WLj+1 to WLk−1, and a group x of word lines WLk to WLn, presetting a relationship that each readout voltage (Vread1, Vread2, . . . , Vready, and Vreadx) corresponding to each group increases toward a bit line side, and applying a readout voltage to a selected word line according to the relationship.
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公开(公告)号：US11070384B2
公开(公告)日：2021-07-20
申请号：US16725486
申请日：2019-12-23
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
Abstract: A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.
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公开(公告)号：US10554422B2
公开(公告)日：2020-02-04
申请号：US15710358
申请日：2017-09-20
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
Abstract: A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.
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公开(公告)号：US10366750B2
公开(公告)日：2019-07-30
申请号：US15861701
申请日：2018-01-04
Applicant: Winbond Electronics Corp.
Inventor： Norio Hattori , Masaru Yano
Abstract: A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.
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公开(公告)号：US20190067325A1
公开(公告)日：2019-02-28
申请号：US16111237
申请日：2018-08-24
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
IPC: H01L27/11582 , H01L27/11568 , H01L27/11575 , G11C16/04
Abstract: A NOR flash memory comprising a memory cell having a three-dimensional structure for saving power consumption is provided. The flash memory of the present invention includes a pillar part, a charge accumulating part, an insulating part, a control gate and a selecting gate. The pillar part extends in a vertical direction from a surface of a substrate and includes a conductive semiconductor material. The charge accumulating part is formed by surrounding the pillar part. The insulating part is formed by surrounding the pillar part. The control gate is formed by surrounding the charge accumulating part. The selecting gate is formed by surrounding the insulating part. One end of the pillar part is electrically connected to a bit line via a contact hole and another one end of the pillar part is electrically connected to a conductive region formed on the surface of the substrate.
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Patent Agency Ranking
公开(公告)号：US20160358929A1
公开(公告)日：2016-12-08
申请号：US15237640
申请日：2016-08-16
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Pin-Yao Wang
IPC: H01L27/115 , H01L21/28 , H01L21/306 , H01L29/66 , H01L21/308
CPC classification number: H01L27/11524 , G11C8/14 , G11C16/12 , H01L21/28273 , H01L21/30604 , H01L21/3085 , H01L29/66553 , H01L29/66825
Abstract: A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).
Abstract translation: 提供一种半导体存储器件的制造方法。 半导体存储器件可以抑制在编程动作期间产生的电流泄漏，从而可以以高可靠性执行编程动作。 本发明的闪存具有形成NAND型串的存储器阵列。 字符串行方向上的存储单元的门通常连接到字线。 位线选择晶体管的栅极通常连接到选择栅极线（SGD）。 源极线选择晶体管的栅极通常连接到选择栅极线（SGS）。 选择栅极线（SGS）的间隔（S4）和与选择栅极线（SGS）相邻的字线（WL0）的栅极大于选择栅极线（SGD）的间隔（S1），并且a 与选择栅线（SGD）相邻的字线（WL7）的栅极。
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公开(公告)号：US09449697B2
公开(公告)日：2016-09-20
申请号：US14621344
申请日：2015-02-12
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Pin-Yao Wang
IPC: G11C11/34 , G11C16/12 , H01L27/115 , G11C8/14
CPC classification number: H01L27/11524 , G11C8/14 , G11C16/12 , H01L21/28273 , H01L21/30604 , H01L21/3085 , H01L29/66553 , H01L29/66825
Abstract: A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).
Abstract translation: 提供一种半导体存储器件，其可以抑制在编程动作期间产生的电流泄漏，使得可以以高可靠性执行编程动作。 本发明的闪存具有形成NAND型串的存储器阵列。 字符串行方向上的存储单元的门通常连接到字线。 位线选择晶体管的栅极通常连接到选择栅极线（SGD）。 源极线选择晶体管的栅极通常连接到选择栅极线（SGS）。 选择栅极线（SGS）的间隔（S4）和与选择栅极线（SGS）相邻的字线（WL0）的栅极大于选择栅极线（SGD）的间隔（S1），并且a 与选择栅线（SGD）相邻的字线（WL7）的栅极。
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公开(公告)号：US20150380092A1
公开(公告)日：2015-12-31
申请号：US14621344
申请日：2015-02-12
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Pin-Yao Wang
IPC: G11C16/12 , H01L27/115 , H01L21/28
CPC classification number: H01L27/11524 , G11C8/14 , G11C16/12 , H01L21/28273 , H01L21/30604 , H01L21/3085 , H01L29/66553 , H01L29/66825
Abstract: A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).
Abstract translation: 提供一种半导体存储器件，其可以抑制在编程动作期间产生的电流泄漏，从而可以以高可靠性执行编程动作。 本发明的闪存具有形成NAND型串的存储器阵列。 字符串行方向上的存储单元的门通常连接到字线。 位线选择晶体管的栅极通常连接到选择栅极线（SGD）。 源极线选择晶体管的栅极通常连接到选择栅极线（SGS）。 选择栅极线（SGS）的间隔（S4）和与选择栅极线（SGS）相邻的字线（WL0）的栅极大于选择栅极线（SGD）的间隔（S1），并且a 与选择栅线（SGD）相邻的字线（WL7）的栅极。
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公开(公告)号：US09196366B2
公开(公告)日：2015-11-24
申请号：US14029807
申请日：2013-09-18
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/26 , G11C16/3409
Abstract: A flash memory with low power consumption and rapid operations is disclosed, including a memory array of memory cells, a word line selection circuit for selecting a row of cells, a current-type sensing circuit electrically connected with each bit line for sensing the current of a selected bit line, and an erase unit erasing the cells in a selected block of the array. The erase unit includes: an erase sequence that determines whether the current of each bit line in the erased block is larger than a first value and ends the erasure if the result is “yes”, and a soft-program sequence that performs a soft program verification, which applies a soft-program voltage to all word lines in the erased block and determines whether the current of each bit line is lower than a second value, and ends the soft programming if the result is “yes”.
Abstract translation: 公开了具有低功耗和快速操作的闪速存储器，包括存储器单元的存储器阵列，用于选择一行单元的字线选择电路，与每个位线电连接以检测电流的电流的电流型感测电路 选择的位线，以及擦除单元的所选块中的单元。 擦除单元包括：擦除序列，其确定擦除块中的每个位线的电流是否大于第一值，并且如果结果为“是”则结束擦除，以及执行软程序的软程序序列 验证，其将软编程电压施加到被擦除块中的所有字线，并确定每个位线的电流是否低于第二值，如果结果为“是”，则结束软编程。
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公开(公告)号：US12198768B2
公开(公告)日：2025-01-14
申请号：US17695852
申请日：2022-03-16
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
Abstract: A semiconductor device and an erasing method may control a number of times an erase pulse. The erasing method of a flash memory includes the following. Multiple sacrificial memory cells in a block are programmed with different write levels first. When a selected block is erased in response to an erase command, a monitor erase pulse (R1) is applied to a well, and then the sacrificial memory cells are verified (S_EV). When the verification fails, a voltage of the monitor erase pulse is increased and then a monitor erase pulse (R2) is applied until the verification of the sacrificial memory cells passes. When the verification is passed, a normal erase pulse (Q1) is applied to the well based on a voltage of the monitor erase pulse (R2) to erase the selected block.
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