公开(公告)号：US20240274196A1

公开(公告)日：2024-08-15

申请号：US18459429

申请日：2023-09-01

申请人： Winbond Electronics Corp.

发明人： Riichiro Shirota

IPC分类号： G11C16/04 ,  G11C5/06 ,  G11C16/14 ,  G11C16/24 ,  H10B41/27 ,  H10B43/27

CPC分类号： G11C16/0483 ,  G11C5/063 ,  G11C16/14 ,  G11C16/24 ,  H10B41/27 ,  H10B43/27

摘要： An AND-type flash memory capable of achieving high integration after providing a miniaturized memory cell size includes: a plurality of diffusion regions (70) formed in a substrate in a column direction, a plurality of gates (20) formed between the opposite diffusion regions (70), a selection control line (SGD), a selection control line (SGS), and a plurality of word lines (WL0 to WLn-1). The selection control line (SGD) is connected to each gate of a bit line side selection transistor. The selection control line (SGS) is connected to each gate of a source line side selection transistor. The word lines (WL0 to WLn-1) are connected to gates of memory cells. Each of the bit line side selection transistor, the source line side selection transistor, and the plurality of memory cells has a channel area in the row direction.

公开(公告)号：US09870828B2

公开(公告)日：2018-01-16

申请号：US15277992

申请日：2016-09-27

申请人： Winbond Electronics Corp.

发明人： Katsutoshi Suito ,  Riichiro Shirota

IPC分类号： G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  H01L27/11524

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3477 ,  H01L27/11524

摘要： An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S100); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S110); performing a erasing verification of the selected memory cell (step S120).

公开(公告)号：US09715935B2

公开(公告)日：2017-07-25

申请号：US14729066

申请日：2015-06-03

申请人： Winbond Electronics Corp.

发明人： Riichiro Shirota

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C11/56 ,  G11C16/16

CPC分类号： G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3445

摘要： A non-volatile semiconductor memory apparatus and a data erasing method thereof are provided to suppress deterioration in reliability due to data rewriting. An erasing method of a flash memory is provided, which includes the following steps. A control gate is maintained at 0V, a high-voltage erase pulse is applied to a P well, such that electrons is emitted from a floating gate to the P well. Then, the control gate is again maintained, and a weak erase pulse with a voltage lower than the erase pulse is applied to the P well.

公开(公告)号：US20160099064A1

公开(公告)日：2016-04-07

申请号：US14729066

申请日：2015-06-03

申请人： Winbond Electronics Corp.

发明人： Riichiro Shirota

IPC分类号： G11C16/14 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3445

摘要： A non-volatile semiconductor memory apparatus and a data erasing method thereof are provided to suppress deterioration in reliability due to data rewriting. An erasing method of a flash memory is provided, which includes the following steps. A control gate is maintained at 0V, a high-voltage erase pulse is applied to a P well, such that electrons is emitted from a floating gate to the P well. Then, the control gate is again maintained, and a weak erase pulse with a voltage lower than the erase pulse is applied to the P well.

摘要翻译： 提供一种非易失性半导体存储装置及其数据擦除方法，以抑制由于数据重写导致的可靠性劣化。 提供了一种闪存的擦除方法，其包括以下步骤。 控制栅极保持在0V，高压擦除脉冲施加到P阱，使得电子从浮动栅极发射到P阱。 然后，再次保持控制栅极，并且将具有低于擦除脉冲的电压的弱擦除脉冲施加到P阱。

公开(公告)号：US11978515B2

公开(公告)日：2024-05-07

申请号：US17179409

申请日：2021-02-19

申请人： Winbond Electronics Corp.

发明人： Riichiro Shirota ,  Masaru Yano

IPC分类号： G11C5/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

摘要： A semiconductor memory device capable of reducing failure caused by a source side effect after a large number of W/E cycles is provided. A reading method of a NAND flash memory includes: dividing multiple word lines connected to each memory cell of a NAND string into a group 1 of word lines WL0 to WLi−1, a group 2 of word lines WLi to WLj, . . . , a group y of word lines WLj+1 to WLk−1, and a group x of word lines WLk to WLn, presetting a relationship that each readout voltage (Vread1, Vread2, . . . , Vready, and Vreadx) corresponding to each group increases toward a bit line side, and applying a readout voltage to a selected word line according to the relationship.

公开(公告)号：US20240071494A1

公开(公告)日：2024-02-29

申请号：US18454051

申请日：2023-08-22

申请人： Winbond Electronics Corp.

发明人： Riichiro Shirota

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  H10B43/35

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/16 ,  H10B43/35

摘要： An AND type flash memory is provided. The AND type flash memory includes a plurality of memory cells connected in parallel between a source line and a bit line. The memory cell includes a charge accumulation layer including a SiN layer serving as a gate insulating film. In case of programming, electrons tunneled from a channel FN are accumulated in the charge accumulation layer of the memory cell. In case of erasing, the electrons accumulated in the charge accumulation layer of the memory cell are released to the channel.

公开(公告)号：US20220028880A1

公开(公告)日：2022-01-27

申请号：US16935199

申请日：2020-07-22

申请人： Winbond Electronics Corp.

发明人： Riichiro Shirota

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C7/18 ,  H01L29/66 ,  H01L29/792

摘要： A NAND flash memory capable of reducing the planar size of a memory cell is provided. The three-dimensional NAND flash memory includes a substrate, an insulating layer, a lower conductive layer (a source), a three-dimensional memory cell structure, and a bit line. The memory cell structure includes a plurality of strip-shaped gate stacks including stacks of insulators and conductors stacked along a vertical direction from the substrate; and a plurality of channel stacks separately arranged along one side of the gate stack. An upper end of the channel stack is electrically connected to the orthogonal bit line, and a lower end of the channel stack is electrically connected to the lower conductive layer.

公开(公告)号：US10811425B2

公开(公告)日：2020-10-20

申请号：US15892350

申请日：2018-02-08

申请人： Winbond Electronics Corp.

发明人： Masaru Yano ,  Riichiro Shirota

IPC分类号： H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/792 ,  H01L21/28

摘要： An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.

公开(公告)号：US20200303384A1

公开(公告)日：2020-09-24

申请号：US16893411

申请日：2020-06-04

申请人： Winbond Electronics Corp.

发明人： Masaru Yano ,  Riichiro Shirota

IPC分类号： H01L27/1157 ,  H01L27/11573 ,  H01L29/792

摘要： An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.

公开(公告)号：US09136004B2

公开(公告)日：2015-09-15

申请号：US14272516

申请日：2014-05-08

申请人： Winbond Electronics Corp.

发明人： Riichiro Shirota

IPC分类号： G11C16/04 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3427

摘要： A programming method for suppressing deterioration of an insulating layer in a memory cell is provided. In the programming method for a flash memory of the invention, a cell unit including programming units that have been programmed is electrically isolated from a bit line; a cell unit not including programming units is electrically coupled with the bit line; a programming voltage is applied to selected word lines; and a pass voltage is applied to non-selected word lines. Moreover, during a period of applying the programming voltage, carriers are generated in a P-well, and hot carriers passing through a depletion region and accelerated by an electric field are injected into the memory cell.

摘要翻译： 提供一种用于抑制存储单元中的绝缘层的劣化的编程方法。 在本发明的闪速存储器的编程方法中，包括已被编程的编程单元的单元单元与位线电隔离; 不包括编程单元的单元单元与位线电耦合; 对所选择的字线施加编程电压; 并且将通过电压施加到未选择的字线。 此外，在施加编程电压的期间，在P阱中产生载流子，通过耗尽区域并通过电场加速的热载流子被注入到存储单元中。