公开(公告)号：US20110105588A1

公开(公告)日：2011-05-05

申请号：US12921477

申请日：2009-03-12

申请人： Frank Y. Xie ,  Xiaodong Yang ,  Ying Liu

发明人： Frank Y. Xie ,  Xiaodong Yang ,  Ying Liu

IPC分类号： A61K31/713 ,  C07H21/02 ,  C12N5/071 ,  C12N15/63 ,  C12N5/10 ,  A61P35/00

CPC分类号： C12N15/1138 ,  C12N2310/14

摘要： The present invention provides siRNA nucleic acid molecules that inhibit Notch1 expression. Methods of using the nucleic acid molecules are also provided.

摘要翻译： 本发明提供抑制Notch1表达的siRNA核酸分子。 还提供了使用核酸分子的方法。

公开(公告)号：US20110085461A1

公开(公告)日：2011-04-14

申请号：US12904786

申请日：2010-10-14

申请人： Ying Liu ,  Valentina Alaria ,  Pere Monclus ,  Sushil Singh

发明人： Ying Liu ,  Valentina Alaria ,  Pere Monclus ,  Sushil Singh

IPC分类号： H04L12/26

CPC分类号： H04L43/12

摘要： A method and a computer-readable storage medium are disclosed for flexible network measurement. Embodiments disclose receiving a network measurement request, transmitting portions of the request to network devices, configuring the network devices to collect metrics from packet data based on the portions of the request, and performing operations to generate metrics as a response to the network measurement request. Embodiments also disclose a flexible, dynamically configurable packet parser. Other embodiments are also disclosed.

摘要翻译： 公开了用于灵活网络测量的方法和计算机可读存储介质。 实施例公开了接收网络测量请求，将该请求的部分传送到网络设备，根据请求的部分配置网络设备以从分组数据收集度量，以及执行操作以产生作为对网络测量请求的响应的度量。 实施例还公开了一种灵活的，动态可配置的分组解析器。 还公开了其他实施例。

公开(公告)号：US20110078641A1

公开(公告)日：2011-03-31

申请号：US12569421

申请日：2009-09-29

申请人： James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

发明人： James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Mechanisms are provided for characterizing long range variability in integrated circuit manufacturing. A model derivation component tests one or more density pattern samples, which are a fabricated integrated circuits having predetermined pattern densities and careful placement of current-voltage (I-V) sensors. The model derivation component generates one or more empirical models to establish range of influence of long range variability effects in the density pattern sample. A variability analysis component receives an integrated circuit design and, using the one or more empirical models, analyzes the integrated circuit design to isolate possible long range variability effects in the integrated circuit design.

摘要翻译： 提供了用于表征集成电路制造中的长距离变化的机制。 模型推导部件测试一个或多个密度样本样本，其是具有预定图案密度的制造的集成电路和电流 - 电压（I-V）传感器的仔细放置。 模型推导组件产生一个或多个经验模型，以确定密度模式样本中长距离变异效应的影响范围。 可变性分析组件接收集成电路设计，并且使用一个或多个经验模型分析集成电路设计以隔离集成电路设计中的可能的长距离变化效应。

公开(公告)号：US07885798B2

公开(公告)日：2011-02-08

申请号：US11746976

申请日：2007-05-10

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Ying Liu ,  Sani R. Nassif ,  Jayakumaran Sivagnaname

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Ying Liu ,  Sani R. Nassif ,  Jayakumaran Sivagnaname

IPC分类号： G06F17/50 ,  G06F7/62

CPC分类号： G06F17/5036

摘要： A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.

摘要翻译： 一种使用网表的电路仿真方法，其中具有未建模的非线性行为的第一器件通过插入具有接近未建模的非线性行为的非线性响应的第二器件而被修改。 第一器件可以是例如第一晶体管，并且第二器件可以是可变电流源，特别是其中电流在表示第一晶体管（栅极至源极或栅极 -排水）。 在仿真电路期间，控制诸如第二晶体管的栅极至源极电压的参数来模拟栅极泄漏。 模型参数可以是第一晶体管技术的栅极的有效量子机械氧化物厚度值的函数。

公开(公告)号：US20110022129A1

公开(公告)日：2011-01-27

申请号：US12741334

申请日：2008-11-05

申请人： Robert K. Prud'homme ,  Marian Gindy ,  Baris Ungun ,  Stephanie Budijono ,  Ying Liu

发明人： Robert K. Prud'homme ,  Marian Gindy ,  Baris Ungun ,  Stephanie Budijono ,  Ying Liu

IPC分类号： A61N5/06 ,  C12N13/00

CPC分类号： A61K9/0009

摘要： Embodiments of the invention include nanoparticulate products of a flash nanoprecipitation process, the products comprising, in combination, pre-formed nanoparticles having properties of an upconversion phosphor and a hydrophobic organic compound having the properties of a photosensitizer, and a method of photodynamic therapy comprising the use of the nanoparticulate products is described.

摘要翻译： 本发明的实施方案包括快速纳米颗粒沉积方法的纳米颗粒产物，该组合物包含具有上转换荧光体和具有光敏剂性质的疏水性有机化合物的特性的预形成纳米颗粒，以及包含 描述了纳米颗粒产品的使用。

公开(公告)号：US20100327892A1

公开(公告)日：2010-12-30

申请号：US12492619

申请日：2009-06-26

申请人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

发明人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

IPC分类号： G01R31/02

CPC分类号： G01R31/2858

摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.

摘要翻译： 提供了一种用于恒流电迁移应力测试的并行阵列架构。 并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。 该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。 此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分 电流源逻辑。 使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

公开(公告)号：US07834649B2

公开(公告)日：2010-11-16

申请号：US12779038

申请日：2010-05-12

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US20100225348A1

公开(公告)日：2010-09-09

申请号：US12779038

申请日：2010-05-12

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US07782076B2

公开(公告)日：2010-08-24

申请号：US12141862

申请日：2008-06-18

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

公开(公告)号：US20090273946A1

公开(公告)日：2009-11-05

申请号：US12290340

申请日：2008-10-28

申请人： Ying Liu ,  Pak-Hong Ng ,  Shou-Lung Chen

发明人： Ying Liu ,  Pak-Hong Ng ,  Shou-Lung Chen

IPC分类号： F21V7/22

CPC分类号： G02F1/133604 ,  G02F1/133605 ,  G02F1/133611

摘要： The present invention provides an illumination module, and a display and a general lighting apparatus using the same. Said illumination module includes a plurality of light guiding strips arranged in juxtaposition with a predefined distance; a plurality of light sources, disposed on at least one end of said light guiding strips respectively for providing the light into said light guiding strips; and a plurality of light reflecting units, disposed between said light guiding strips for reflecting the light from said light guiding strips. The light reflecting units according to the present invention can guide the light from the sides of light guiding strips or other light not toward the right side of the illumination module back to the right side of the illumination module, and thus improving the light output efficiency and uniformity.

摘要翻译： 本发明提供了一种照明模块，以及使用其的显示器和一般照明装置。 所述照明模块包括以预定距离并列布置的多个导光条; 多个光源，分别设置在所述导光条的至少一端，用于将光提供到所述导光条中; 以及多个光反射单元，设置在所述导光条之间，用于反射来自所述导光条的光。 根据本发明的光反射单元可以将来自导光条或其他光的侧面的光引导到照明模块的右侧，直到照明模块的右侧，从而提高光输出效率， 均匀性