公开(公告)号：US06812103B2

公开(公告)日：2004-11-02

申请号：US10175774

申请日：2002-06-20

申请人： Hongmei Wang ,  Zhongze Wang

发明人： Hongmei Wang ,  Zhongze Wang

IPC分类号： H01L21336

CPC分类号： H01L29/66628 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66636

摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.

摘要翻译： 本发明提供了一种制造MOSFET中的电介质塞的技术。 通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。 然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及源极之间的沟道区域 和漏区。

公开(公告)号：US06744102B2

公开(公告)日：2004-06-01

申请号：US10087416

申请日：2002-02-27

申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Rongsheng Yang

IPC分类号： H01L2994

CPC分类号： H01L21/823462

摘要： In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms. Transistor gates are formed over the first and second gate dielectric layers, and then p-type source/drain regions are formed proximate the transistor gates in the first area and n-type source/drain regions are formed proximate the transistor gates in the second area.

摘要翻译： 根据本发明的一个方面，形成场效应晶体管的半导体处理方法包括在被配置用于形成p型场效应晶体管的第一区域上形成第一栅极电介质层，以及第二区域，用于形成n型场效应 晶体管，半导体衬底上的两个区域。 第一栅极电介质层是在第一栅极介电层内的氮浓度为0.1％摩尔至10.0％摩尔浓度的二氧化硅，与另一个高度位置相比，在一个高度位置处的第一栅极介电层内的氮原子的浓度较高 。 第一栅介质层在第二区域上被移除，同时在第一区域上留下第一栅极介质层，并且在第二区域上形成第二栅极电介质层。 第二栅极电介质层是基本上不含氮原子的二氧化硅材料。 在第一和第二栅极电介质层上形成晶体管栅极，然后在第一区域中的晶体管栅极附近形成p型源极/漏极区域，并且在第二区域中的晶体管栅极附近形成n型源极/漏极区域 。

公开(公告)号：US06555455B1

公开(公告)日：2003-04-29

申请号：US09146296

申请日：1998-09-03

申请人： Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

发明人： Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

IPC分类号： H01L213205

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/3144 ,  H01L21/76202 ,  H01L21/76895 ,  H01L21/823481 ,  Y10S438/909

摘要： A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz. The device structure may be subjected to a rapid thermal process in a nitrogen containing atmosphere or, alternatively, an atmosphere devoid of nitrogen.

摘要翻译： 在器件结构的高温处理期间，防止在半导体器件结构内形成氧化钛的方法包括形成钝化层以阻止在半导体器件结构的钛/氧化物界面处形成氧化钛。 该方法包括提供至少包括氧化物区域并在氧化物区域的表面上形成钛层的衬底组件。 在形成钛层之前，用包含氮的等离子体处理氧化物区域表面，以形成形成钛层的钝化层。 在衬底组件上进行热处理，其中钝化层在衬底组件的热处理期间基本上抑制氧从氧化物层的扩散。 通常，钝化层包括SixOyNz。 装置结构可以在含氮气氛中进行快速热处理，或者在没有氮的气氛中进行快速热处理。

公开(公告)号：US06548383B1

公开(公告)日：2003-04-15

申请号：US09441912

申请日：1999-11-17

申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Michael P. Violette

发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Michael P. Violette

IPC分类号： H01L21425

CPC分类号： H01L21/823892

摘要： In accordance with an aspect of the invention, a twin-well method of forming CMOS integrated circuitry having first and second conductivity type gates includes conducting a first conductivity type well implant, a second conductivity type well implant, a first conductivity type gate implant and a second conductivity type gate implant using no more than two masking steps. In another aspect of the invention, a twin well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates includes conducting a first conductivity type well implant and a second conductivity type gate implant in a common masking step.

摘要翻译： 根据本发明的一个方面，形成具有第一和第二导电类型栅极的CMOS集成电路的双阱方法包括：导电第一导电类型阱注入，第二导电类型阱注入，第一导电型栅极注入和 使用不超过两个掩模步骤的第二导电类型栅极注入。 在本发明的另一方面，形成具有第一和第二导电类型晶体管栅极的CMOS集成电路的双阱法包括在公共掩模步骤中传导第一导电类型阱注入和第二导电类型栅极注入。

公开(公告)号：US06503805B2

公开(公告)日：2003-01-07

申请号：US09741776

申请日：2000-12-19

申请人： Zhongze Wang ,  Rongsheng Yang

发明人： Zhongze Wang ,  Rongsheng Yang

IPC分类号： H01L21336

CPC分类号： H01L29/66537 ,  H01L21/2652 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/66575

摘要： A field effect transistor having a doped region in the substrate immediately underneath the gate of the transistor and interposed between the source and drain of the transistor is provided. The doped region has a retrograde dopant profile such that the doping concentration immediately adjacent the gate is selected to allow for the formation of a channel when a threshold voltage is applied to the gate thereby eliminating the need for an enhancement doping step during formation of the transistor. The retrograde doping profile increases with the depth into the substrate which inhibits stray currents from traveling between the source and drain of the transistor in the absence of the formation of a channel as a result of voltage being applied to the gate of the transistor.

摘要翻译： 提供了在晶体管的栅极正下方具有位于晶体管的源极和漏极之间的衬底中的掺杂区域的场效应晶体管。 掺杂区域具有逆向掺杂剂分布，使得紧邻栅极的掺杂浓度被选择为允许在阈值电压施加到栅极时形成沟道，从而在形成晶体管期间不需要增强掺杂步骤 。 逆向掺杂分布随着衬底的深度而增加，其在由于施加到晶体管的栅极的电压的结果而没有形成沟道的情况下，抑制杂散电流在晶体管的源极和漏极之间传播。

公开(公告)号：US20120256682A1

公开(公告)日：2012-10-11

申请号：US13372160

申请日：2012-02-13

申请人： Jeffrey Herbert Fischer ,  Manish Garg ,  Zhongze Wang

发明人： Jeffrey Herbert Fischer ,  Manish Garg ,  Zhongze Wang

IPC分类号： G06F17/50 ,  H01L25/00

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.

摘要翻译： 提供了用于在设计和制造集成电路期间进行选择性推送处理以改善集成电路的选定电路的性能的方法和装置。 一种示例性方法包括识别集成电路布局的关键部分，该集成电路布局定义了具有关键工作频率要求的功能元件，并且在关键部分中设计子电路以使能执行速度推动过程以增加子电路的性能。 该方法还可以包括在关键部分和在关键部分之外的集成电路的一部分之间的边界处识别供电节点，时钟供应节点和接口节点中的至少一个。 关键部分可以被设计成具有独立于在关键部分之外的集成电路的部分的功率域。

公开(公告)号：US08194478B2

公开(公告)日：2012-06-05

申请号：US12699933

申请日：2010-02-04

申请人： Haining Yang ,  Zhongze Wang ,  ChangHo Jung

发明人： Haining Yang ,  Zhongze Wang ,  ChangHo Jung

IPC分类号： G11C7/00

CPC分类号： G11C8/16 ,  G11C11/412

摘要： A multiple-port RAM circuit has a data-in line coupled to multiple bit lines and multiple bit line bars. The circuit also has multiple word lines. A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller than enables the word lines to substantially simultaneously write a value from the bit lines to the memory cell.

摘要翻译： 多端口RAM电路具有耦合到多个位线和多个位线条的数据输入线。 电路也有多条字线。 存储单元耦合到位线，位线条和字线。 电路还包括控制器，使得字线能够基本上同时从位线写入存储单元。

公开(公告)号：US07816246B2

公开(公告)日：2010-10-19

申请号：US11499134

申请日：2006-08-03

申请人： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

发明人： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

IPC分类号： H01L21/8234 ,  H01L21/44

CPC分类号： H01L21/76888 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride layer, on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

摘要翻译： 用于集成电路和半导体器件的保险丝及其使用方法。 半导体熔丝在绝缘基板上包含两层导电层，一层覆盖和下层的难熔金属氮化物层。 可以在制造包括相同材料的局部互连结构的过程中制造半导体熔丝。 可以用于编程冗余电路的保险丝可以由电流而不是激光束吹扫，从而允许熔丝宽度小于由激光束熔断的现有技术的熔丝。 熔断器也可能被吹过比吹出具有相似尺寸的常规多晶硅保险丝所需的电流更小的电流。

公开(公告)号：US07314812B2

公开(公告)日：2008-01-01

申请号：US10651314

申请日：2003-08-28

申请人： Zhongze Wang

发明人： Zhongze Wang

IPC分类号： H01L21/04

CPC分类号： H01L29/518 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28194

摘要： A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.

摘要翻译： 提供了一种用于在掺杂剂注入和激活之后使用氮注入和退火来降低栅极氧化物的有效厚度的方法。 更具体地说，本发明提供一种用于制造半导体器件的方法，例如晶体管，其包括硬化的栅极氧化物，其特征可以在多晶硅/栅极氧化物界面处具有相对较大的氮浓度， 栅极氧化物和栅极氧化物/衬底界面处。 另外，本发明提供了一种用于制造半导体器件的方法，该半导体器件具有设置在其多晶硅层上的金属栅极带（例如，金属硅化物层），该器件包括硬化的栅极氧化物，并且其特征可以是相对较大的氮 在硅化物/多晶硅界面处的浓度基本上防止交叉扩散。

公开(公告)号：US06974757B2

公开(公告)日：2005-12-13

申请号：US10607869

申请日：2003-06-27

申请人： Zhongze Wang

发明人： Zhongze Wang

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L29/786 ,  H01L21/30

CPC分类号： H01L29/66772 ,  H01L21/76256 ,  H01L29/78603

摘要： A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer. A method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry. After the nitridizing, a field effect transistor gate is formed operably proximate the silicon comprising layer. Other methods are disclosed. Integrated circuitry is contemplated regardless of the method of fabrication.

摘要翻译： 形成绝缘体上硅包括集成电路的晶片接合方法包括氮化器件晶片的硅的外表面的至少一部分。 在氮化之后，器件晶片与处理晶片接合。 一种形成绝缘体上硅的方法，包括集成电路包括将包含绝缘体上硅电路的硅层的界面氮化为绝缘体上硅电路的绝缘体层。 在氮化之后，场效应晶体管栅极可靠地形成在包含硅的层上。 公开了其他方法。 无论制造方法如何，都可以考虑集成电路。