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    Home Network System
    41.
    发明申请
    Home Network System 审中-公开
    家庭网络系统

    公开(公告)号：US20080027566A1

    公开(公告)日：2008-01-31

    申请号：US10560253

    申请日：2004-05-28

    Applicant: Seung-Myun Baek ,  Koon-Seok Lee ,  Hwan-Jong Choi ,  Yong-Tae Kim ,  Feel-Young Koo ,  Ja-In Koo ,  Seong-Hwan Kang

    Inventor： Seung-Myun Baek ,  Koon-Seok Lee ,  Hwan-Jong Choi ,  Yong-Tae Kim ,  Feel-Young Koo ,  Ja-In Koo ,  Seong-Hwan Kang

    IPC: H04L29/06 ,  G06F17/00

    CPC classification number: H04L43/00 ,  H04L12/2803 ,  H04L12/2818 ,  H04L12/2825 ,  H04L43/0817 ,  H04L2012/2849

    Abstract: The present invention discloses a home network system (100) which uses a message structure for efficient communication between a plurality of home appliances. The home network system (100) includes at least one slave device (60, 70, 80), and at least one master device (50) connected to the slave device (60, 70, 80) through a network (90), for transmitting a request message to the slave device (60, 70, 80), wherein the request message is transmitted from an upper layer of the master device (50) to a lower layer thereof and from a lower layer of the slave device (60, 70, 80) to an upper layer thereof, and has a command code implying an operation which will be executed by the slave device (60, 70, 80), and a related argument for executing the operation.

    Abstract translation: 本发明公开了一种家庭网络系统（100），其使用消息结构来在多个家用电器之间进行有效的通信。 家庭网络系统（100）包括至少一个从设备（60,70,80）以及通过网络（90）连接到从设备（60,70,80）的至少一个主设备（50），用于 向所述从设备（60,70,80）发送请求消息，其中所述请求消息从所述主设备（50）的上层发送到其下层，并且从所述从设备（60， 70,80）到其上层，并且具有指示将由从设备（60,70,80）执行的操作的命令代码和用于执行该操作的相关参数。

    Method of manufacturing a semiconductor device having a switching function
    42.
    发明授权
    Method of manufacturing a semiconductor device having a switching function 有权
    具有切换功能的半导体装置的制造方法

    公开(公告)号：US07297596B2

    公开(公告)日：2007-11-20

    申请号：US11552359

    申请日：2006-10-24

    Applicant: Sung-Sam Lee ,  Yong-Tae Kim ,  Mi-Youn Kim ,  Gyo-Young Jin ,  Dae-Won Ha ,  Yun-Gi Kim

    Inventor： Sung-Sam Lee ,  Yong-Tae Kim ,  Mi-Youn Kim ,  Gyo-Young Jin ,  Dae-Won Ha ,  Yun-Gi Kim

    IPC: H01L21/336

    CPC classification number: H01L21/823437 ,  H01L21/823481

    Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

    Abstract translation: 提供能够抑制空穴迁移的半导体器件。 半导体器件包括在基本上垂直于字线延伸的第二方向的第一方向上延伸的虚拟区域。 此外，隔离层图案可以不在第二方向上切割伪区域。 因此，防止虚拟区域的倾斜和空隙迁移。 还提供了制造半导体器件的方法。

    Nonvolatile memory device and method of fabricating the same
    43.
    发明申请
    Nonvolatile memory device and method of fabricating the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US20070170491A1

    公开(公告)日：2007-07-26

    申请号：US11698658

    申请日：2007-01-26

    Applicant: Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

    Inventor： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

    IPC: H01L29/788

    CPC classification number: H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

    Abstract: a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

    Abstract translation: 非易失性存储器件包括限定在半导体衬底中的有源区和跨越有源区的控制栅电极。 栅极绝缘层介于控制栅极电极和活性电极之间。 在有源区中形成浮栅，以穿透控制栅电极并延伸到预定深度进入半导体衬底。 隧道绝缘层被连续插入在控制栅电极和浮栅之间以及半导体衬底和浮栅之间。 可以在通过顺序蚀刻控制栅极导电层和半导体衬底形成沟槽之后形成浮置栅极，并且在控制栅极导电层的沟槽和侧壁上形成隧道绝缘层。 浮动栅极形成在沟槽中，以延伸到预定深度进入半导体衬底。

    Flash memory device and method of manufacturing the same
    45.
    发明申请
    Flash memory device and method of manufacturing the same 审中-公开
    闪存装置及其制造方法

    公开(公告)号：US20070111451A1

    公开(公告)日：2007-05-17

    申请号：US11650237

    申请日：2007-01-05

    Applicant: Jae-Hwang Kim ,  Yong-Suk Choi ,  Seung-Beom Yoon ,  Yong-Tae Kim ,  Young-Sam Park

    Inventor： Jae-Hwang Kim ,  Yong-Suk Choi ,  Seung-Beom Yoon ,  Yong-Tae Kim ,  Young-Sam Park

    IPC: H01L21/336

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/40114 ,  H01L29/42328

    Abstract: A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.

    Abstract translation: 提供一种包括隧道介电层，浮栅，层间电介质层和形成在半导体衬底上的至少两个模层的闪存器件及其制造方法。 通过顺序地图案化这些层，形成彼此对准的第一模具层图案和浮动栅极层图案。 选择性地横向蚀刻第一模具层图案的侧表面的暴露部分，从而在其侧壁中形成具有凹槽的第一模具层第二图案。 栅极电介质层形成在与浮动栅层图案相邻的半导体衬底上。 具有由第二模层图案中的凹槽确定的宽度的控制栅极形成在栅介质层上。 通过去除第一模具层第二图案，在控制门的侧壁上形成间隔物。 使用间隔物作为蚀刻掩模来选择性地蚀刻层间电介质层和浮栅层图案的暴露部分，以形成具有由沟槽和间隔物的宽度限定的宽度的浮动栅极。

    Flash memory device and method of manufacturing the same
    46.
    发明授权
    Flash memory device and method of manufacturing the same 有权

    公开(公告)号：US07192833B2

    公开(公告)日：2007-03-20

    申请号：US11025279

    申请日：2004-12-29

    Applicant: Jae-Hwang Kim ,  Yong-Suk Choi ,  Seung-Beom Yoon ,  Yong-Tae Kim ,  Young-Sam Park

    Inventor： Jae-Hwang Kim ,  Yong-Suk Choi ,  Seung-Beom Yoon ,  Yong-Tae Kim ,  Young-Sam Park

    IPC: H01L21/336

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42328

    Abstract: A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.

    Multi-layered, UV-cured polymer electrolyte and lithium secondary battery comprising the same
    48.
    发明授权
    Multi-layered, UV-cured polymer electrolyte and lithium secondary battery comprising the same 有权
    多层，紫外线固化的聚合物电解质和包含其的锂二次电池

    公开(公告)号：US07135254B2

    公开(公告)日：2006-11-14

    申请号：US10275383

    申请日：2001-01-31

    Applicant: Kyung-Suk Yun ,  Byung-Won Cho ,  Won-Il Cho ,  Hyung-Sun Kim ,  Un-Sek Kim ,  Hee-Woo Rhee ,  Yong-Tae Kim

    Inventor： Kyung-Suk Yun ,  Byung-Won Cho ,  Won-Il Cho ,  Hyung-Sun Kim ,  Un-Sek Kim ,  Hee-Woo Rhee ,  Yong-Tae Kim

    IPC: H01M6/18

    CPC classification number: H01M10/0565 ,  H01M2/1653 ,  H01M2/1666 ,  H01M2/1686 ,  H01M6/164 ,  H01M6/168 ,  H01M10/052 ,  H01M2300/0085

    Abstract: The present invention relates to a multi-layered, UV-cured polymer electrolyte and lithium secondary battery comprising the same, wherein the polymer electrolyte comprises: A) a separator layer formed of polymer electrolyte, PP, PE, PVdF or non-woven fabric, wherein the separator layer having two surfaces; B) at least one gelled polymer electrolyte layer located on at least one surface of the separator layer comprising: a) polymer obtained by curing ethyleneglycoldi(meth)acrylate oligomer of the formula (I) by UV irradiation: CH2═CR1COO(CH2CH2O)nCOCR2═CH2 wherein, R1 and R2 are independently hydrogen or methyl group, and n is a integer of 3–20; and b) at least one polymer selected from the group consisting of PVdF-based polymer, PAN-based polymer, PMMA-based polymer and PVC-based polymer; and C) organic electrolyte solution in which lithium salt is dissolved in a solvent.

    Abstract translation: 本发明涉及包含该聚合物电解质的多层紫外线固化的聚合物电解质和锂二次电池，其中所述聚合物电解质包括：A）由聚合物电解质，PP，PE，PVdF或无纺布形成的隔离层， 其中所述隔离层具有两个表面; B）位于分离器层的至少一个表面上的至少一个胶凝聚合物电解质层，包括：a）通过UV照射固化式（I）的乙二醇二（甲基）丙烯酸酯低聚物获得的聚合物：CH 2 CO 2（CH 2 CH 2 CH 2）n CO 2 CH 2 CO 2（CH 2 CH 2 CH 2） 其中，R 1和R 2各自独立地为氢或甲基，n为3-20的整数; 和b）至少一种选自PVdF基聚合物，PAN基聚合物，基于PMMA的聚合物和基于PVC的聚合物的聚合物; 和C）其中锂盐溶解在溶剂中的有机电解质溶液。

    Non-volatile memory device, methods of fabricating and operating the same
    49.
    发明申请
    Non-volatile memory device, methods of fabricating and operating the same 失效
    非易失性存储器件，其制造和操作方法

    公开(公告)号：US20060170028A1

    公开(公告)日：2006-08-03

    申请号：US11323355

    申请日：2005-12-30

    Applicant: Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

    Inventor： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

    IPC: H01L29/76

    CPC classification number: H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

    Abstract: A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

    Abstract translation: 非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极 通过隧道绝缘层引起电荷隧穿。 选择栅电极与控制栅电极绝缘。 根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

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