公开(公告)号：US5323355A

公开(公告)日：1994-06-21

申请号：US923998

申请日：1992-09-22

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G11C7/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/1033 ,  G11C8/18

摘要： A semiconductor memory device according to the invention includes a memory cell array (8) connected to a data bus through a first selector circuit (6), a second selector circuit (7) responsive to a first control signal (.phi. 0, .phi. X), a third selector circuit (8) responsive to a second control signal (.phi. 1 to .phi. 8), a row address buffer (17) responsive to activation of a row address strobe signal, an address fetching circuit (21) for instructing fetching of a column address every time of a specified number of toggled CAS signals, a column address buffer (19) responsive to a third control signal from the address fetching circuit (21), a nibble decoder (38) for generating the first and the second control signals, and a gate control circuit (39). A column address used to access a next memory cell is fetched during an activating period of the row address strobe signal after the column address is fetched.

摘要翻译： PCT No.PCT / JP92 / 00048 Sec。 371日期：1992年9月22日 102（e）1992年9月22日PCT PCT 1992年1月22日PCT公布。 公开号WO92 / 13348 根据本发明的半导体存储器件包括通过第一选择器电路（6）连接到数据总线的存储单元阵列（8），响应于第一控制信号的第二选择器电路（7） （phi 0，phi X），响应于第二控制信号（phi 1至phi 8）的第三选择器电路（8），响应于行地址选通信号的激活的行地址缓冲器（17），地址提取电路 （21），用于指示每当指定数量的切换的CAS信号每次获取列地址时，响应于来自地址取出电路（21）的第三控制信号的列地址缓冲器（19），一个四位解码器（38），用于 产生第一和第二控制信号，以及门控制电路（39）。 在取出列地址之后，在行地址选通信号的激活期间，取出用于访问下一个存储单元的列地址。

公开(公告)号：US5239508A

公开(公告)日：1993-08-24

申请号：US730723

申请日：1991-07-16

申请人： Hidenori Nomura ,  Yoshiharu Kato ,  Eisaku Itoh

发明人： Hidenori Nomura ,  Yoshiharu Kato ,  Eisaku Itoh

IPC分类号： G11C11/409 ,  G11C7/10 ,  H03F1/30

CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051

摘要： A semiconductor memory device comprises a memory cell array including a plurality of memory cells, a plurality of word lines and bit lines connected to the memory cells, a data bus for carrying data to be written in and/or read out from a selected memory cell, an addressing circuit for selecting one of the word lines and bit lines, an input buffer for outputting the electric signal indicative of the data to be written on the data bus, a current-mirror amplifier connected to the data bus for amplifying the electric signals that are read out from the memory cell on the data bus, and a limiter circuit connected to the data bus for limiting a voltage swing of the electric signals on the data bus. The limiter circuit maintains the data bus at a predetermined voltage level and limits the voltage level of the electric signals supplied to the current-mirror amplifier, wherein the limiter circuit changes the predetermined voltage level in response to a voltage level of a supply voltage that powers the current-mirror amplifier.

公开(公告)号：USD324375S

公开(公告)日：1992-03-03

申请号：US521466

申请日：1990-05-09

申请人： Yoshiharu Kato ,  Chitose Ono

设计人： Yoshiharu Kato ,  Chitose Ono

公开(公告)号：US4537865A

公开(公告)日：1985-08-27

申请号：US629846

申请日：1984-07-11

申请人： Shinsei Okabe ,  Hiroshi Komatsu ,  Yukio Hamaji ,  Shozo Kojima ,  Yoshiharu Kato

发明人： Shinsei Okabe ,  Hiroshi Komatsu ,  Yukio Hamaji ,  Shozo Kojima ,  Yoshiharu Kato

IPC分类号： C01G23/00 ,  C01G25/00 ,  C04B35/468 ,  C04B35/46

CPC分类号： B82Y30/00 ,  C01G23/003 ,  C01G25/006 ,  C04B35/4684 ,  C01P2004/02 ,  C01P2004/50 ,  C01P2004/62 ,  C01P2004/64

摘要： A process for preparing a particulate ceramic material comprising the steps of:(a) adding carbon dioxide or an aqueous solution of a soluble carbonate to first aqueous solution of a nitrate or chloride of Ba, Sr, Ca or Mg in a first vessel to adjust the pH of said first aqueous solution to between 7 and 10 thereby forming a carbonate precipitate;(b) adding an aqueous solution of a soluble hydroxide to a second aqueous solution of a nitrate or chloride of Ti, Zr, Sn or Pb in a second vessel to adjust the pH of said second aqueous solution to between 7 and 10 thereby forming a hydroxide precipitate;(c) combining slurries containing the precipitates formed in said first and second vessels;(d) mixing the combined slurries;(e) passing the slurries through a filter;(f) washing the filter cake with water;(g) drying the filter cake to form a powder;(h) calcining the dried powder; and(i) grinding the calcined powder.

摘要翻译： 一种制备颗粒状陶瓷材料的方法，包括以下步骤：（a）在第一容器中将二氧化碳或可溶性碳酸盐水溶液加入到Ba，Sr，Ca或Mg的硝酸盐或氯化物的第一水溶液中以调节 所述第一水溶液的pH为7至10，由此形成碳酸盐沉淀物; （b）在第二容器中将可溶性氢氧化物的水溶液加入到Ti，Zr，Sn或Pb的硝酸盐或氯化物的第二水溶液中以将所述第二水溶液的pH调节至7至10，从而形成 氢氧化物沉淀; （c）组合含有形成在所述第一和第二容器中的沉淀物的浆料; （d）混合组合的浆料; （e）使浆料通过过滤器; （f）用水清洗滤饼; （g）干燥滤饼以形成粉末; （h）煅烧干粉; 和（i）研磨煅烧粉末。

公开(公告)号：US09206546B2

公开(公告)日：2015-12-08

申请号：US13318232

申请日：2010-04-28

申请人： Yoshiharu Kato ,  Katsumi Sakamoto

发明人： Yoshiharu Kato ,  Katsumi Sakamoto

IPC分类号： D06M23/10 ,  D06M11/76 ,  D06M15/564 ,  D06M15/70 ,  D06M23/00 ,  D06M23/08 ,  D06N3/14 ,  B32B7/12 ,  B32B27/12 ,  B32B27/40

CPC分类号： D06M23/10 ,  B32B7/12 ,  B32B27/12 ,  B32B27/40 ,  B32B2307/54 ,  B32B2307/724 ,  B32B2307/7265 ,  D06M11/76 ,  D06M15/564 ,  D06M15/70 ,  D06M23/00 ,  D06M23/08 ,  D06M2200/12 ,  D06N3/14 ,  D06N2205/24 ,  D06N2207/06 ,  D06N2207/08 ,  D06N2209/123 ,  D06N2209/128

摘要： A moisture-permeable waterproof fabric which has a well-balanced combination of moisture permeability and waterproofing properties and has excellent strength, in particular, tensile strength, is provided without increasing environmental burden. A synthetic-polymer solution comprising a synthetic polymer consisting mainly of a polyurethane, fine inorganic particles, and a polar organic solvent is applied to one surface of a fibrous fabric and then brought into contact with a gaseous phase in which waterdrops having an average particle diameter of 1-30 μm have been evenly dispersed, thereby making the synthetic polymer semisolid. The fabric is then immersed in water to completely solidify the polymer and thereby obtain a moisture-permeable waterproof fabric comprising the fibrous fabric and, united to one surface thereof, a microporous film of a single-layer structure comprising the synthetic polymer consisting mainly of a polyurethane (the number of micropores having a pore diameter of 0.1-5 μm is (5-200)×104/mm2 in a vertical cross-section, and the film has a tensile strength of 3-80 MPa, a moisture permeability as measured by the calcium chloride method of 6,000 g/m2·24 hr or higher or a moisture permeability as measured by the potassium acetate method of 6,000 g/m2·24 hr or higher, and a water pressure resistance of 60 kPa or higher).

摘要翻译： 具有良好的透湿性和防水性的组合的透湿性防水布，具有优异的强度，特别是拉伸强度，而不会增加环境负担。 将包含主要由聚氨酯，无机微粒和极性有机溶剂组成的合成聚合物的合成聚合物溶液施加到纤维织物的一个表面上，然后与气相接触，其中具有平均粒径 均匀分散，从而制成合成聚合物半固体。 然后将织物浸入水中以完全固化聚合物，从而获得包含纤维织物的透湿性防水织物，并且在其一个表面上与单一结构的微孔膜结合，其包含主要由 聚氨酯（垂直截面中孔径为0.1-5μm的微孔数为（5-20​​0）×104 / mm2），该膜的拉伸强度为3-80MPa，测得的透湿度 通过6,000g / m 2·24小时以上的氯化钙法或通过醋酸钾法测定的透水性为6,000g / m 2·24hr以上，耐水压性为60kPa以上）。

公开(公告)号：US08711643B2

公开(公告)日：2014-04-29

申请号：US13300033

申请日：2011-11-18

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/02 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： A memory interface circuit includes a gating circuit that starts detection of a logic level of a data strobe signal in accordance with a data read command. A clamp circuit clamps the data strobe signal to a first logic level after the data read command is issued. A detection circuit detects a logic level of the data strobe signal, which is driven by the memory, in accordance with the data read command.

摘要翻译： 存储器接口电路包括门控电路，其根据数据读取命令开始检测数据选通信号的逻辑电平。 在发出数据读取命令之后，钳位电路将数据选通信号钳位到第一逻辑电平。 检测电路根据数据读取命令检测由存储器驱动的数据选通信号的逻辑电平。

公开(公告)号：US08023353B2

公开(公告)日：2011-09-20

申请号：US12818956

申请日：2010-06-18

申请人： Masami Nakashima ,  Yoshiharu Kato ,  Kazufumi Komura

发明人： Masami Nakashima ,  Yoshiharu Kato ,  Kazufumi Komura

IPC分类号： G11C7/00

CPC分类号： G11C29/50016 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/028 ,  G11C29/50 ,  G11C29/783 ,  G11C2207/2227 ,  G11C2211/4061 ,  G11C2211/4067

摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

摘要翻译： 本发明提供一种由于适当的刷新稀疏功能而在待机状态下减少电流消耗的半导体存储器件及其刷新控制方法。 当刷新操作和外部访问操作彼此独立地执行时添加刷新稀疏功能时，刷新地址计数器输出刷新地址Add（C）并将预定的高位比特输入到刷新 - 作为高阶刷新地址的输出控制Add（C）（m），其中进行关于刷新操作的判断。 与判断结果相对应的刷新允许信号RFEN被输入到字驱动器以激活和控制字驱动器。 刷新稀疏控制电路的判断处理可嵌入行系统的访问时间。

公开(公告)号：US07551612B2

公开(公告)日：2009-06-23

申请号：US09277213

申请日：1999-03-26

申请人： Yasusi Kobayashi ,  Yoshihiro Watanabe ,  Hiroshi Nishida ,  Masami Murayama ,  Naoyuki Izawa ,  Yasuhiro Aso ,  Yoshihiro Uchida ,  Hiromi Yamanaka ,  Jin Abe ,  Yoshihisa Tsuruta ,  Yoshiharu Kato ,  Satoshi Kakuma ,  Shiro Uriu ,  Noriko Samejima ,  Eiji Ishioka ,  Shigeru Sekine ,  Yoshiyuki Karakawa ,  Atsushi Kagawa ,  Mikio Nakayama ,  Miyuki Kawataka ,  Satoshi Esaka ,  Nobuyuki Tsutsui ,  Fumio Hirase ,  Atsuko Suzuki ,  Shouji Kohira ,  Kenichi Okabe ,  Takashi Hatano ,  Yasuhiro Nishikawa ,  Jun Itoh ,  Shinichi Araya

发明人： Yasusi Kobayashi ,  Yoshihiro Watanabe ,  Hiroshi Nishida ,  Masami Murayama ,  Naoyuki Izawa ,  Yasuhiro Aso ,  Yoshihiro Uchida ,  Hiromi Yamanaka ,  Jin Abe ,  Yoshihisa Tsuruta ,  Yoshiharu Kato ,  Satoshi Kakuma ,  Shiro Uriu ,  Noriko Samejima ,  Eiji Ishioka ,  Shigeru Sekine ,  Yoshiyuki Karakawa ,  Atsushi Kagawa ,  Mikio Nakayama ,  Miyuki Kawataka ,  Satoshi Esaka ,  Nobuyuki Tsutsui ,  Fumio Hirase ,  Atsuko Suzuki ,  Shouji Kohira ,  Kenichi Okabe ,  Takashi Hatano ,  Yasuhiro Nishikawa ,  Jun Itoh ,  Shinichi Araya

IPC分类号： H04L12/66

CPC分类号： H04L5/16 ,  H04L2012/5628 ,  H04L2012/5645 ,  H04L2012/5652 ,  H04Q11/0478

摘要： A switch station including an ATM switch; a memory storing control data for operations of the switch station; an intra-station device, accommodating a subscriber line, performing communication operation on subscriber ATM cell; a control processor generating control information in link access protocol (LAP) format; and an interface unit converting LAP control information into ATM cell to the intra-station device through the ATM switch, wherein the control information is communicated according to LAP, the intra-station device receives the control information and transmits a direct memory access request to obtain control data stored in the memory, the interface unit obtains and converts the data format of the control data into ATM cell to transmit to the intra-station device through the switch, and the intra-station device performs the communication operation on the subscriber ATM cell based on the control data received through the switch.

摘要翻译： 包括ATM交换机的交换台; 存储用于所述开关站的操作的控制数据的存储器; 站内设备，容纳用户线路，对用户ATM信元进行通信操作; 控制处理器生成链路接入协议（LAP）格式的控制信息; 以及接口单元，其通过ATM交换机将LAP控制信息转换为ATM信元到站内设备，其中根据LAP传送控制信息，站内设备接收控制信息并发送直接存储器访问请求以获得 存储在存储器中的控制数据，接口单元获取控制数据的数据格式并将其转换成ATM信元，通过交换机发送到站内设备，并且站内设备对用户ATM信元进行通信操作 基于通过交换机接收的控制数据。

公开(公告)号：US20070097776A1

公开(公告)日：2007-05-03

申请号：US11640906

申请日：2006-12-19

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G11C8/00

CPC分类号： G11C5/06

摘要： There is provided memory control device and memory control method, which can prevent wiring complication by many crossing wirings, and reduction of yield and quality. When a memory control device CC1 selects a memory chip CC2, an internal circuit of a select circuit 27 is changed by a switch signal SWS2. In this case, the changeover is made so that a select signal S2 outputted from an internal circuit 40 is inputted to a predetermined memory terminal of the memory chip CC2. The select signal S2 is inputted to the corresponding predetermined memory terminal of the memory chip CC2, and thereby, the memory chip CC2 is activated, and set to a state capable of inputting and outputting control signals 21 to 25. The control signals 21 to 25 are assigned to control terminals P21 to P27 after being hanged by the select circuit 27 in signal sequence corresponding to terminal array sequence of memory terminals 21a to 27a of the memory chip CC2.

摘要翻译： 提供了存储器控制装置和存储器控制方法，可以防止多条交叉布线的布线复杂化，降低产量和质量。 当存储器控制装置CC 1选择存储器芯片CC 2时，选择电路27的内部电路被切换信号SWS2改变。在这种情况下，进行切换，使得从内部输出的选择信号S 2 电路40被输入到存储器芯片CC 2的预定存储器端子。选择信号S 2被输入到存储器芯片CC 2的对应的预定存储器端子，由此存储器芯片CC 2被激活，并被设置为 一个能够输入和输出控制信号21至25的状态。控制信号21至25被分配给控制端P21至P27，在选择电路27以对应于存储器端子21a的端子阵列序列的信号序列 到27位的内存芯片CC 2。

公开(公告)号：US20070090695A1

公开(公告)日：2007-04-26

申请号：US11583131

申请日：2006-10-19

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： H02B1/24

CPC分类号： H03K5/26 ,  G11C11/401 ,  G11C29/02 ,  G11C29/023 ,  Y10T307/74

摘要： An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of testing the semiconductor device. In response to a data strobe signal TDQS for testing, the delay circuits DC0 and DC1 produce delay data strobe signals IDQS0 and IDQS1 delayed by delay times DT0 and DT1. Outputted as a reverse signal from the inverter INV0, is a reverse data strobe signal RIDQS0 in response to the delay data strobe signal IDQS0, and delayed by an allowable delay time IT. Inputted into the NAND gate ND0, are the reverse data strobe signal RIDQS0 and the delay data strobe signal IDQS1. When, in comparison with the phase of the delay data strobe signal IDQS0, the phase of the delay data strobe signal IDQS1 is delayed by the allowable delay time IT or more, a pulse signal PL0 is not outputted from the NAND gate ND0.

摘要翻译： 目的是提供一种半导体器件，其中可以确定由延迟电路给出的微小延迟时间是否在规定值内，以及测试半导体器件的方法。 响应于用于测试的数据选通信号TDQS，延迟电路DC 0和DC 1产生延迟数据选通信号IDQS 0和IDQS 1延迟延迟时间DT 0和DT 1。 作为来自反相器INV 0的反向信号输出，是响应于延迟数据选通信号IDQS 0的反向数据选通信号RIDQS 0，并延迟了允许的延迟时间IT。 输入到NAND门ND 0中的是反向数据选通信号RIDQS 0和延迟数据选通信号IDQS 1。 当与延迟数据选通信号IDQS 0的相位相比，延迟数据选通信号IDQS 1的相位延迟可允许的延迟时间IT或更多时，不从NAND门ND输出脉冲信号PL 0 0。