公开(公告)号：US06545753B2

公开(公告)日：2003-04-08

申请号：US09893186

申请日：2001-06-27

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton

IPC分类号： G01N2100

CPC分类号： H01L21/7681 ,  G01N21/4738 ,  H01J37/32935

摘要： A system for monitoring and/or controlling an etch process associated with a dual damascene process via scatterometry based processing is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the desirability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor produces a real time feed forward information to control the etch process, in particular, terminating the etch process when desired end points have been encountered.

摘要翻译： 提供了一种用于通过基于散射测量的处理来监测和/或控制与双镶嵌工艺相关联的蚀刻工艺的系统。 该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。 从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。 所收集的光指示在晶片的各个部分实现的蚀刻结果。 测量系统向处理器提供蚀刻相关数据，该处理器确定晶片的相应部分的蚀刻的可取性。 该系统还包括一个或多个蚀刻装置，每个这样的装置对应于晶片的一部分并提供其蚀刻。 处理器产生实时前馈信息以控制蚀刻工艺，特别是在遇到所需端点时终止蚀刻工艺。

公开(公告)号：US06534243B1

公开(公告)日：2003-03-18

申请号：US10000493

申请日：2001-10-23

申请人： Michael K. Templeton ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Kathleen R. Early ,  Ursula Q. Quinto

发明人： Michael K. Templeton ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Kathleen R. Early ,  Ursula Q. Quinto

IPC分类号： G03F7039

CPC分类号： G03F7/405 ,  G03F7/0035 ,  G03F7/40

摘要： In one embodiment, the present invention relates to a method of treating a patterned resist involving providing the patterned resist having a first number of structural features, the patterned resist comprising an acid catalyzed polymer; contacting a coating containing a coating material, at least one basic compound, a photoacid generator, and a dye with the patterned resist; irradiating the coated patterned resist; permitting a deprotection region to form within an inner portion of the patterned resist; and removing the coating and the deprotection region to provide a second number of patterned resist structural features, wherein the first number is smaller than the second number.

摘要翻译： 在一个实施方案中，本发明涉及一种处理图案化抗蚀剂的方法，包括提供具有第一数目的结构特征的图案化抗蚀剂，所述图案化抗蚀剂包含酸催化聚合物; 使含有涂层材料的涂层，至少一种碱性化合物，光致酸发生剂和染料与图案化的抗蚀剂接触; 照射经涂覆的图案化抗蚀剂; 允许在图案化抗蚀剂的内部部分内形成去保护区; 并且去除涂层和去保护区域以提供第二数量的图案化抗蚀剂结构特征，其中第一数目小于第二数量。

公开(公告)号：US06495435B2

公开(公告)日：2002-12-17

申请号：US09788246

申请日：2001-02-15

申请人： Michael K. Templeton ,  Hao Fang ,  Maria C. Chan

发明人： Michael K. Templeton ,  Hao Fang ,  Maria C. Chan

IPC分类号： H01L2120

CPC分类号： H01L27/11521 ,  H01L21/76838 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115

摘要： A method and system for providing a plurality of lines in a semiconductor memory device is disclosed. The method and system include providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask. The method and system also preferably include removing a second portion of the layer of material exposed by the pattern of the physical mask to form the plurality of lines.

摘要翻译： 公开了一种用于在半导体存储器件中提供多条线的方法和系统。 该方法和系统包括提供半导体衬底，提供多条线并提供相邻特征。 多条线包括与相邻特征相邻的相邻线。 多条线中的每条线具有对于多根线中的每条线基本相同的线宽度。 优选地，利用掩模形成多条线以打印多条线和相邻特征的物理掩模。 掩模包括用于相邻行的至少第一多边形和用于相邻特征的至少第二多边形之间的掩模辅助特征。 掩模辅助特征具有足够大的尺寸以影响相邻线的宽度，并且足够小以防止相应的特征被印刷在物理掩模上。 该方法和系统还优选地包括去除由物理掩模的图案暴露的材料层的第二部分以形成多条线。

公开(公告)号：US06459482B1

公开(公告)日：2002-10-01

申请号：US09729294

申请日：2000-12-04

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

IPC分类号： G01J110

CPC分类号： H01J37/28 ,  H01J2237/2826

摘要： The present invention provides SEM systems, SEM calibration standards, and SEM calibration methods that improved accuracy in critical dimension measurements. The calibration standards have features formed with an amorphous material such as amorphous silicon. Amorphous materials lack the crystal grain structure of materials such as polysilicon and are capable of providing sharper edged features and higher accuracy patterns than grained materials. The amorphous material can be bound to a silicon wafer substrate through an intermediate layer of material, such as silicon dioxide. Where the intermediate layer is insulating material, as is silicon dioxide, the intermediate layer may be patterned with gaps to provide for electrical communication between the amorphous silicon and the silicon wafer. Charges imparted to the amorphous silicon during electron beam scanning may thereby drain to the silicon wafer rather than accumulating to a level where they would distort the electron beam.

摘要翻译： 本发明提供SEM系统，SEM校准标准和SEM校准方法，提高了临界尺寸测量的精度。 校准标准品具有非晶体材料如非晶硅形成的特征。 无定形材料缺乏诸如多晶硅的材料的晶粒结构，并且能够提供比颗粒材料更尖锐的边缘特征和更高精度的图案。 非晶材料可以通过诸如二氧化硅的材料的中间层与硅晶片衬底结合。 在中间层是绝缘材料的情况下，如二氧化硅那样，中间层可以用间隙图案化以提供非晶硅和硅晶片之间的电连通。 因此，在电子束扫描期间赋予非晶硅的电荷可以从而被排出到硅晶片，而不是积聚到它们会使电子束变形的水平。

公开(公告)号：US06445072B1

公开(公告)日：2002-09-03

申请号：US09617158

申请日：2000-07-17

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton ,  Bharath Rangarajan

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton ,  Bharath Rangarajan

IPC分类号： H01L214763

CPC分类号： H01L21/7682 ,  Y10S977/897

摘要： One aspect of the present invention relates to a method of forming an innerlayer dielectric, involving the steps of providing a substrate having at least two metal lines thereon; providing a conformal insulation layer over the substrate and metal lines; forming a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; at least one of thinning and planarizing the second insulation layer; and forming a third insulation layer over the second insulation layer. Another aspect of the present invention relates to an innerlayer dielectric semiconductor structure, containing a semiconductor substrate having at least two metal lines thereon; a conformal insulation layer over the semiconductor substrate and metal lines, the conformal insulation layer having a substantially uniform thickness from about 250 Å to about 5,000 Å; a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; and a third insulation layer over the second insulation layer.

摘要翻译： 本发明的一个方面涉及一种形成内层电介质的方法，包括以下步骤：提供其上具有至少两条金属线的基底; 在衬底和金属线上提供保形绝缘层; 在所述保形绝缘层上形成第二绝缘层，所述第二绝缘层包含位于两条金属线之间的空隙; 将所述第二绝缘层变薄和平坦化的至少一个; 以及在所述第二绝缘层上形成第三绝缘层。 本发明的另一方面涉及一种内层电介质半导体结构，其包含其上具有至少两条金属线的半导体衬底; 半导体衬底和金属线上的共形绝缘层，保形绝缘层具有从大约至大约等于的大致均匀的厚度; 在保形绝缘层之上的第二绝缘层，所述第二绝缘层包含位于两个金属线之间的空隙; 以及在所述第二绝缘层上的第三绝缘层。

公开(公告)号：US06354133B1

公开(公告)日：2002-03-12

申请号：US09729293

申请日：2000-12-04

申请人： Sanjay K. Yedur ,  Bhanwar Singh ,  Bryan K. Choo ,  Michael K. Templeton ,  Ramkumar Subramanian

发明人： Sanjay K. Yedur ,  Bhanwar Singh ,  Bryan K. Choo ,  Michael K. Templeton ,  Ramkumar Subramanian

IPC分类号： G01B528

CPC分类号： G01Q40/02 ,  G01Q40/00 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/849 ,  Y10S977/85 ,  Y10S977/876 ,  Y10S977/901

摘要： The present invention provides systems, methods, and standards for calibrating nano-measuring devices. Calibration standards of the invention include carbon nanotubes and methods of the invention involve scanning carbon nanotubes using nano-scale measuring devices. The widths of the carbon nanotube calibration standards are known with a high degree of accuracy. The invention allows calibration of a wide variety of nano-scale measuring devices, taking into account many, and in some cases all, of the systematic errors that may affect a nano-scale measurement. The invention may be used to accurately calibrate line width, line height, and trench width measurements and may be used to precisely characterize both scanning probe microscope tips and electron microscope beams.

摘要翻译： 本发明提供了用于校准纳米测量装置的系统，方法和标准。 本发明的校准标准包括碳纳米管，本发明的方法涉及使用纳米级测量装置扫描碳纳米管。 碳纳米管校准标准品的宽度以高精度已知。 考虑到可能影响纳米尺度测量的许多系统误差以及在所有这些系统误差中，本发明允许校准各种各样的纳米尺度的测量装置。 本发明可以用于精确校准线宽，线高度和沟槽宽度测量，并且可以用于精确地表征扫描探针显微镜尖端和电子显微镜束。

公开(公告)号：US06326231B1

公开(公告)日：2001-12-04

申请号：US09207562

申请日：1998-12-08

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Sanjay K. Yedur ,  Marina V. Plat ,  Christopher F. Lyons ,  Bharath Rangarajan ,  Michael K. Templeton

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Sanjay K. Yedur ,  Marina V. Plat ,  Christopher F. Lyons ,  Bharath Rangarajan ,  Michael K. Templeton

IPC分类号： H01L2100

CPC分类号： H01L21/32139 ,  H01L21/0276 ,  H01L21/3143 ,  H01L21/3145

摘要： In one embodiment, the present invention relates to a method of forming a silicon oxynitride antireflection coating over a metal layer, involving the steps of providing a semiconductor substrate comprising the metal layer over at least part of the semiconductor substrate; depositing a silicon oxynitride layer over the metal layer having a thickness from about 100 Å to about 150 Å; and forming an oxide layer having a thickness from about 5 Å to about 50 Å over the silicon oxynitride layer to provide the silicon oxynitride antireflection coating. In another embodiment, the present invention relates to a method of reducing an apparent reflectivity of a metal layer having a first reflectivity in a semiconductor structure, involing forming a silicon oxynitride antireflection coating over the metal layer; wherein the silicon oxynitride antireflection coating formed over the metal layer has a second reflectivity and is formed by depositing silicon oxynitride on the metal layer by chemical vapor deposition and forming an oxide layer over the oxynitride, and the difference between the first reflectivity and the second reflectivity is at least about 60%.

摘要翻译： 在一个实施方案中，本发明涉及在金属层上形成氮氧化硅抗反射涂层的方法，包括以下步骤：在半导体衬底的至少一部分上提供包括金属层的半导体衬底; 在所述金属层上沉积厚度为约至约的氧氮化硅层; 并在氮氧化硅层上形成厚度约为5-20埃的氧化物层，以提供氮氧化硅抗反射涂层。 在另一个实施方案中，本发明涉及一种在半导体结构中减少具有第一反射率的金属层的表观反射率的方法，包括在金属层上形成氮氧化硅抗反射涂层; 其中形成在所述金属层上的所述氧氮化硅抗反射涂层具有第二反射率，并且通过化学气相沉积在所述金属层上沉积氧氮化硅并在所述氧氮化物上形成氧化物层，并且所述第一反射率和所述第二反射率之间的差异 至少约60％。

公开(公告)号：US06316804B1

公开(公告)日：2001-11-13

申请号：US09569721

申请日：2000-05-11

申请人： Michael K. Templeton ,  Kathleen R. Early

发明人： Michael K. Templeton ,  Kathleen R. Early

IPC分类号： H01L29788

CPC分类号： H01L27/11521

摘要： A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions. After removing the silicon nitride layer portions, and exposing the polysilicon layer portions, the implanted structure is annealed and made ready for forming the self-aligned floating gate MOS structures, or other semiconductor structure on the conductive material pads. The floating gates may be formed having a minimal width with respect to an underlying active region.

摘要翻译： 一种半导体装置和制造方法，用于在用于形成自对准的浮置栅极MOS结构或其它半导体器件的半导体衬底中形成氧化物隔离区。 该方法包括提供预制的半导体衬底构件，其具有制造在多晶硅层上的阻挡氧化物层，多晶硅层和多个间隔开的氮化硅层部分。 氮化物层部分描绘用于形成自对准浮置栅极MOS结构的区域，以及描绘未被多个氮化硅层部分保护的二氧化硅层的部分和所述多晶硅层的部分。 该方法还包括将氧O 2离子注入到衬底的区域中的步骤，包括二氧化硅层的那些未受保护的部分和多晶硅层的部分以形成氧化物隔离区。 在去除氮化硅层部分并暴露多晶硅层部分之后，将注入结构退火并准备好在导电材料焊盘上形成自对准浮栅MOS结构或其它半导体结构。 浮动栅极可以形成为相对于下面的有源区域具有最小宽度。

公开(公告)号：US06197455B1

公开(公告)日：2001-03-06

申请号：US09231679

申请日：1999-01-14

申请人： Sanjay K. Yedur ,  Bharath Rangarajan ,  Bhanwar Singh ,  Michael K. Templeton ,  Kathleen R. Early

发明人： Sanjay K. Yedur ,  Bharath Rangarajan ,  Bhanwar Singh ,  Michael K. Templeton ,  Kathleen R. Early

IPC分类号： G03F900

CPC分类号： G03F1/74 ,  Y10S977/856 ,  Y10S977/859

摘要： A method of repairing defects in a photomask used in the formation of a semiconductor wafer includes the use of a scanning tunneling microscope. The scanning tunneling microscope includes a very sharp tip having a diameter on the order of 100 Å or less. In order to remove excess material from a mask layer in the photomask, the tip is placed into contact with those regions having such excess material and the tip is used to scrape the excess material away. In order to add material to voids in a mask layer of the photomask, the tip is placed in proximity to those areas in need of the excess material and caused to deposit such material upon, for example, application of a bias voltage to the tip.

摘要翻译： 修复用于形成半导体晶片的光掩模中的缺陷的方法包括使用扫描隧道显微镜。 扫描隧道显微镜包括具有大约等于或小于100埃的直径的非常锋利的尖端。 为了从光掩模中的掩模层去除多余的材料，将尖端放置成与具有这种多余材料的那些区域接触，并且尖端用于刮除多余的材料。 为了向光掩模的掩模层中的空隙添加材料，将尖端放置在需要多余材料的那些区域附近，并且使得将这种材料沉积在例如向尖端施加偏置电压。

公开(公告)号：US6066530A

公开(公告)日：2000-05-23

申请号：US57992

申请日：1998-04-09

申请人： Michael K. Templeton ,  Kathleen R. Early

发明人： Michael K. Templeton ,  Kathleen R. Early

IPC分类号： H01L21/8247 ,  H01L21/336

CPC分类号： H01L27/11521

摘要： A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O.sub.2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions. After removing the silicon nitride layer portions, and exposing the polysilicon layer portions, the implanted structure is annealed and made ready for forming the self-aligned floating gate MOS structures, or other semiconductor structure on the conductive material pads. The floating gates may be formed having a minimal width with respect to an underlying active region.

摘要翻译： 一种半导体装置和制造方法，用于在用于形成自对准的浮置栅极MOS结构或其它半导体器件的半导体衬底中形成氧化物隔离区。 该方法包括提供预制的半导体衬底构件，其具有制造在多晶硅层上的阻挡氧化物层，多晶硅层和多个间隔开的氮化硅层部分。 氮化物层部分描绘用于形成自对准浮置栅极MOS结构的区域，以及描绘未被多个氮化硅层部分保护的二氧化硅层的部分和所述多晶硅层的部分。 该方法还包括将氧O 2离子注入到衬底的区域中的步骤，包括二氧化硅层的那些未受保护的部分和多晶硅层的部分以形成氧化物隔离区。 在去除氮化硅层部分并暴露多晶硅层部分之后，将注入结构退火并准备好在导电材料焊盘上形成自对准浮栅MOS结构或其它半导体结构。 浮动栅极可以形成为相对于下面的有源区域具有最小宽度。