公开(公告)号：US07435628B1

公开(公告)日：2008-10-14

申请号：US11881671

申请日：2007-07-27

申请人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

发明人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter Johnson

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L21/823885 ,  H01L21/823487 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.

摘要翻译： 垂直MOS晶体管具有垂直堆叠的源极区域，沟道区域和漏极区域以及从漏极区域的顶表面延伸穿过漏极区域，沟道区域并且部分地延伸到源极区域的沟槽 。 垂直MOS晶体管还具有对沟槽进行排列的绝缘层，以及接触绝缘层以填充沟槽的导电栅极区域。

公开(公告)号：US20080213959A1

公开(公告)日：2008-09-04

申请号：US12012545

申请日：2008-02-04

申请人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko

发明人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L29/42324

摘要： An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.

摘要翻译： 在非易失性存储器（NVM）单元结构中提供电屏蔽，以在编程操作期间保护电池的浮动栅极免受在浮动栅极附近的电荷再分配的任何影响。 可以从覆盖浮动栅极的第二多晶硅层或其他导电材料产生屏蔽。 屏蔽可能接地。 或者，其可以连接到电池的控制栅电极，从而在浮栅和控制栅之间形成更好的耦合。 屏蔽罩完全不需要覆盖浮动栅极，如果与围绕浮动栅极的电介质层的耦合减小，则实现必要的保护效果。

公开(公告)号：US07339835B1

公开(公告)日：2008-03-04

申请号：US11057355

申请日：2005-02-14

申请人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko

发明人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko

IPC分类号： G11C11/34

CPC分类号： G11C16/14

摘要： Feedback between the floating gate voltage and a high erase voltage is utilized in the erase operation of a non-volatile memory (NVM) cell. Erasing stops when the floating gate voltage reaches the threshold voltage of the controlling transistor, making the variability of the NVM cell's threshold voltage the same as a regular device in the integrated circuit structure, thereby reducing the significant threshold voltage variability in erased NVM cells.

摘要翻译： 在非易失性存储器（NVM）单元的擦除操作中，利用浮栅电压和高擦除电压之间的反馈。 当浮动栅极电压达到控制晶体管的阈值电压时，擦除停止，使得NVM单元的阈值电压的变化与集成电路结构中的常规器件相同，从而降低了擦除的NVM单元中的显着阈值电压变化。

公开(公告)号：US07298599B1

公开(公告)日：2007-11-20

申请号：US10917605

申请日：2004-08-13

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski ,  Philip Lindorpher

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski ,  Philip Lindorpher

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： A snapback ESD protection network coupled across first and second integrated circuit pads and including first and second snapback devices, such as SCR devices, with the second device having a turnoff current ITOFF which is greater than the turnoff current of the first device. Each of the snapback devices has an anode terminal and a cathode terminal, with the first device anode and cathode terminals being coupled to the respective first and second integrated circuit pads through a first effective series resistance and the second device being coupled to the respective first and second integrated circuit pads through a second effective series resistance, with the first effective series resistance being smaller than the second so as to cause the first and second snapback devices to tend to turn on at about the same time at the beginning of an ESD event. The differences in turnoff current cause the second snapback device to turn off prior to the first snapback device at the conclusion of an ESD event.

摘要翻译： 耦合在第一和第二集成电路焊盘上并且包括第一和第二快速恢复装置（例如SCR装置）的快速恢复ESD保护网络，其中第二装置具有大于截止电流的截止电流I TOFF < 的第一个设备。 每个快速恢复装置具有阳极端子和阴极端子，其中第一器件阳极和阴极端子通过第一有效串联电阻耦合到相应的第一和第二集成电路焊盘，并且第二器件耦合到相应的第一和 第二集成电路焊盘通过第二有效串联电阻，其中第一有效串联电阻小于第二有效串联电阻，以便使得第一和第二快速恢复装置在ESD事件开始时大致同时导通。 在ESD事件结束时，截止电流之间的差异导致第二个恢复装置在第一个恢复装置之前关闭。

公开(公告)号：US07141831B1

公开(公告)日：2006-11-28

申请号：US10900709

申请日：2004-07-28

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski

IPC分类号： H01L29/74

CPC分类号： H01L27/0262

摘要： An SCR device having a first P type region disposed in a semiconductor body and electrically connected to anode terminal of the device. At least one N type region is also disposed in the body adjacent the first P type region so as to form a PN junction having a width Wn near a surface of the semiconductor body. A further P type region is also disposed in the body to form a further PN junction with the N type region, with the junction having a width Wp near the body surface, with Wp being at least 1.5 times width Wn. A further N type region is provided which is electrically connected to a cathode terminal of the device and forming a third PN junction with the further N type region.

摘要翻译： 一种SCR器件，其具有设置在半导体本体中并与该器件的阳极端子电连接的第一P型区域。 至少一个N型区域也设置在与第一P型区域相邻的本体中，以便形成在半导体本体的表面附近具有宽度Wn的PN结。 另外的P型区域还设置在主体中以与N型区域形成另外的PN结，其中接合部在身体表面附近具有宽度Wp，Wp为宽度Wn的至少1.5倍。 提供另外的N型区域，其电连接到器件的阴极端子，并与另外的N型区域形成第三PN结。

公开(公告)号：US07050314B1

公开(公告)日：2006-05-23

申请号：US10625961

申请日：2003-07-23

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski ,  Philipp Lindorfer

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski ,  Philipp Lindorfer

IPC分类号： H02M3/18

CPC分类号： H02M3/07

摘要： A charge pump circuit in which at least one of the switching elements takes the form of a LVTSCR. The switching on and off of the LVTSCRs may be achieved by making use of a pulsed input and relying on the triggering and holding voltages of the LVTSCRs to switch on and off.

摘要翻译： 一种电荷泵电路，其中至少一个开关元件采取LVTSCR的形式。 LVTSCR的接通和断开可以通过使用脉冲输入并依靠LVTSCR的触发和保持电压来接通和关断来实现。

公开(公告)号：US06982907B1

公开(公告)日：2006-01-03

申请号：US11044965

申请日：2005-01-27

申请人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko

发明人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C2216/26

摘要： A programming technique for a one-time-programmable non-volatile memory (NVM) utilizes a repeated programming cycle with an interval between cycles that is long enough to redistribute charge in the layers surrounding the floating gate of the cell. Each cycle programs the floating gate and also the surrounding layers. The cycling saturates in an equilibrium state when the electric field form outside to the floating gate equals zero. This technique eliminates the first stage of conventional VT drop in NVM cells and, thus, improves retention.

摘要翻译： 用于一次性可编程非易失性存储器（NVM）的编程技术利用重复的编程周期，其周期之间的间隔足够长以重新分布围绕该单元的浮动栅极的层中的电荷。 每个循环都对浮动门和周围的层进行编程。 当电场外部到浮动门等于零时，循环饱和状态处于平衡状态。 这种技术消除了NVM单元中常规VT下降的第一阶段，从而改善了保留。

公开(公告)号：US06903978B1

公开(公告)日：2005-06-07

申请号：US10664469

申请日：2003-09-17

申请人： Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter J. Hopper

发明人： Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter J. Hopper

IPC分类号： G11C16/12 ,  G11C16/04

CPC分类号： G11C16/12

摘要： A method of programming a PMOS stacked gate memory cell is provided that utilizes a sequence of control gate pulses to obtain the desired potential on the floating gate.

摘要翻译： 提供了一种编程PMOS堆叠栅极存储单元的方法，其利用一系列控制栅极脉冲来获得浮置栅极上的期望电位。

公开(公告)号：US20120230118A1

公开(公告)日：2012-09-13

申请号：US13477019

申请日：2012-05-21

申请人： Jeffrey A. Babcock ,  Yuri Mirgorodski ,  Natalia Lavrovskaya ,  Saurabh Desai

发明人： Jeffrey A. Babcock ,  Yuri Mirgorodski ,  Natalia Lavrovskaya ,  Saurabh Desai

IPC分类号： G11C16/10

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7841 ,  H01L29/7881

摘要： The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.

摘要翻译： 可以通过利用局部加热元件来使得非易失性存储器（NVM）被编程和擦除的次数大大增加，所述局部加热元件在NVM被编程和擦除时使隧道电荷载体损坏的氧化物退火。 在编程和擦除之前，加热元件的热​​量时，编程和擦除电压也会降低。

公开(公告)号：US07964485B1

公开(公告)日：2011-06-21

申请号：US12589417

申请日：2009-10-23

申请人： William French ,  Erika Mazotti ,  Yuri Mirgorodski

发明人： William French ,  Erika Mazotti ,  Yuri Mirgorodski

IPC分类号： H01L21/22

CPC分类号： H01L29/0847 ,  H01L21/2253 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.

摘要翻译： 用于形成半导体器件的掺杂区域的方法包括用掩模掩蔽衬底的一部分。 掩模被配置为在掺杂区域内产生渐变掺杂分布。 该方法还包括使用掩模执行植入物以在衬底中产生掺杂区域和未掺杂区域。 该方法还包括扩散掺杂区域以在掺杂区域中产生渐变掺杂分布。 掩模可以包括具有分布在整个光致抗蚀剂材料中的开口的第一区域，其中开口的尺寸和间隔变化。 掩模还可以包括具有分布在整个开放区域中的光致抗蚀剂材料块的第二区域，其中光刻胶块的尺寸和间距变化。 扩散掺杂区域可以包括施加高温退火以使掺杂和未掺杂区域平滑以产生线性渐变的掺杂分布。