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    Media item relighting technique
    41.
    发明授权
    Media item relighting technique 有权

    公开(公告)号：US10475392B2

    公开(公告)日：2019-11-12

    申请号：US15063373

    申请日：2016-03-07

    申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

    发明人： Niranjan Thanikachalam ,  Loic Arnaud Baboulaz ,  Damien Firmenich ,  Sabine Suesstrunk ,  Martin Vetterli

    IPC分类号： G09G3/34 ,  G09G5/10

    摘要： The present invention concerns a method of method of relighting a media item comprising media elements. The method comprises, for at least some of the media elements: determining, in a first signal domain, a light transport function describing the appearance of a particular media element under different illumination conditions at least partly defined by positions of a light source used to illuminate the particular media element; sampling, in the first signal domain, the light transport function of the particular media element to obtain discrete data samples of the light transport function; projecting the data samples in the first signal domain into a sampling grid to obtain spatially sparsely and non-uniformly sampled light transport function; interpolating, in a second signal domain, the sparsely and non-uniformly sampled light transport function to obtain an approximate light transport matrix in the second signal domain; converting the approximate light transport matrix into the first signal domain to obtain an approximate substantially uniformly sampled light transport function in the first signal domain; and using, in the first signal domain, the approximate substantially uniformly light transport function to relight the media item.

    Sample processing device with detachable slide
    43.
    发明授权
    Sample processing device with detachable slide 有权

    公开(公告)号：US10436683B2

    公开(公告)日：2019-10-08

    申请号：US14381084

    申请日：2013-02-15

    申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

    发明人： Ata Tuna Ciftlik ,  Martin Gijs

    IPC分类号： B01L3/00 ,  G01N1/31 ,  G01N33/574

    摘要： A biological and chemical sample processing device that b. comprises a high pressure-resistant, shallow and wide area microfluidic chamber having at least one wall formed by a detachable slide containing samples such as immobilized entities, biological samples or molecules, c. comprises an arrangement of microfluidic access holes for injecting to and collecting fluid form said chamber, d. is interfaced with inlet ports and microfluidic channels which are formed external to the chamber, e. is configured so that the slide may be brought into contact with the device to form the said chamber, f. is adapted to deliver and to transport fluidic substances and reagents inside said chamber in a fast manner, preferably within less than 15 seconds, and in a regular or uniform way owing to said arrangement of microfluidic access holes.

    Organizing neural networks
    44.
    发明授权
    Organizing neural networks 有权

    公开(公告)号：US10387767B2

    公开(公告)日：2019-08-20

    申请号：US13566128

    申请日：2012-08-03

    申请人： Henry Markram ,  Rodrigo de Campos Perin ,  Thomas K. Berger

    发明人： Henry Markram ,  Rodrigo de Campos Perin ,  Thomas K. Berger

    IPC分类号： G06N3/04 ,  G06F3/08 ,  G06N3/08

    摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for organizing trained and untrained neural networks. In one aspect, a neural network device includes a collection of node assemblies interconnected by between-assembly links, each node assembly itself comprising a network of nodes interconnected by a plurality of within-assembly links, wherein each of the between-assembly links and the within-assembly links have an associated weight, each weight embodying a strength of connection between the nodes joined by the associated link, the nodes within each assembly being more likely to be connected to other nodes within that assembly than to be connected to nodes within others of the node assemblies.

    Boolean logic optimization in majority-inverter graphs
    45.
    发明授权
    Boolean logic optimization in majority-inverter graphs 有权

    公开(公告)号：US10380309B2

    公开(公告)日：2019-08-13

    申请号：US14727114

    申请日：2015-06-01

    申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

    发明人： Luca Gaetano Amarù ,  Pierre-Emmanuel Julien Marc Gaillardon ,  Giovanni De Micheli

    IPC分类号： G06F17/50

    摘要： We present a Boolean logic optimization framework based on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. Current MIG optimization is supported by a consistent algebraic framework. However, when algebraic methods cannot improve a result quality, stronger Boolean methods are needed to attain further optimization. For this purpose, we propose MIG Boolean methods exploiting the error masking property of majority operators. Our MIG Boolean methods insert logic errors that strongly simplify an MIG while being successively masked by the voting nature of majority nodes. Thanks to the data-structure/methodology fitness, our MIG Boolean methods run in principle as fast as algebraic counterparts. Experiments show that our Boolean methodology combined with state-of-art MIG algebraic techniques enable superior optimization quality. For example, when targeting depth reduction, our MIG optimizer transforms a ripple carry adder into a carry look-ahead one. Considering the set of IWLS'05 (arithmetic intensive) benchmarks, our MIG optimizer reduces by 17.98% (26.69%) the logic network depth while also enhancing size and power activity metrics, with respect to ABC academic optimizer. Without MIG Boolean methods, i.e., using MIG algebraic optimization alone, the previous gains are halved. Employed as front-end to a delay-critical 22-nm ASIC flow (logic synthesis+physical design) our MIG optimizer reduces the average delay/area/power by (15.07%, 4.93%, 1.93%), over 27 academic and industrial benchmarks, as compared to a leading commercial ASIC flow.