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41.发明授权公开(公告)号：US11601753B2
公开(公告)日：2023-03-07
申请号：US17344907
申请日：2021-06-10
Inventor： Hsin-Yuan Chiu , Tsung-Fu Lin
Abstract: A parametric equalizer includes an equalizer circuit, a first protection circuit, a second protection circuit, and a first addition circuit. The equalizer circuit is arranged to receive an input signal, and process the input signal to generate an output signal. The first protection circuit is arranged to generate a first protection signal according to the output signal, the input signal, and a first processed signal. The second protection circuit is arranged to generate a second protection signal according to the input signal and a second processed signal. The first addition circuit is coupled to the first protection circuit and the second protection circuit, and is arranged to combine the first protection signal and the second protection signal to generate an equalizer output signal.
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42.发明授权公开(公告)号：US11570563B1
公开(公告)日：2023-01-31
申请号：US17382393
申请日：2021-07-22
Inventor： Jung-Kuei Chang , Wun-Long Yu
IPC: H04R29/00 , H04B17/309
Abstract: A loudspeaker controller for estimating a fundamental resonance frequency of a loudspeaker includes: an amplifier circuit, arranged to generate a driving signal of the loudspeaker according to an audio input signal; a sensing circuit, arranged to sense characteristics of the driving signal to generate a measurement signal; a plurality of band pass filter circuits, arranged to filter the measurement signal to generate a plurality of filter outputs, respectively, wherein the plurality of band pass filter circuits have different passbands; and an estimation circuit, arranged to estimate the fundamental resonance frequency according to the plurality of filter outputs.
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公开(公告)号：US11489499B1
公开(公告)日：2022-11-01
申请号：US17396853
申请日：2021-08-09
Inventor： Tsung-Fu Lin , Hsin-Yuan Chiu
Abstract: A switch circuit provides a first output signal and a second output signal for switching between ternary modulation and quaternary modulation for a target device. A first output signal is provided from one of a first signal, a second signal and a ground signal according to an input signal and a duty signal, wherein the first signal is generated through performing a one-bit left-shift operation for the input signal, and the second signal is generated through adding the input signal and the duty signal. A second output signal is provided from one of a third signal, a fourth signal and the ground signal according to the input signal and the duty signal, wherein the third signal is generated through subtracting the input signal from the duty signal, and the fourth signal is generated through performing a two's-complement transformation and the one-bit left-shift operation for the input signal.
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公开(公告)号：US11482952B1
公开(公告)日：2022-10-25
申请号：US17496747
申请日：2021-10-07
Inventor： Shih-Chieh Wang , Yong-Yi Jhuang , Ming-Fu Tsai
Abstract: A method for determining zero crossing occurrence in an alternating current (AC) signal with constant frequency of a permanent magnet synchronous motor (PMSM) includes: sampling the AC signal to obtain a plurality of data points; starting to count a number of consecutive data points that have sampled values with a same sign in a detection range, to generate a count value, wherein the consecutive data points are included in the plurality of data points; determining whether the count value is equal to a zero crossing determination value; and in response to the count value being equal to the zero crossing determination value, determining that a zero crossing occurs at a last data point of the consecutive data points.
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45.发明申请公开(公告)号：US20220223213A1
公开(公告)日：2022-07-14
申请号：US17149689
申请日：2021-01-14
Inventor： MING-XUN WANG , CHIH-HAO CHEN , JI-JR LUO
Abstract: A post over-erase correction (POEC) method with an auto-adjusting verification mechanism and a leakage degree detection function detects gm degradation or leakage degree of flash cells before or after entering the POEC process. When a preset condition is satisfied, the auto-adjusting verification mechanism of the POEC is switched on to further reduce leakage current. After cycling, the POEC repairs Vt of over-erased cells to a higher level to solve leakage issues. The erase shot count increases due to slower erase speeds after cycling. Therefore, the cycling degree of flash cells is detected by observing the shot number that the erase operation used. When the leakage phenomenon becomes serious, the bit line (BL) leakage current, amount of repaired BLs, and over-erase correction (OEC) shot number will increase during the OEC procedure. Therefore, the leakage degree of flash cells can be detected by inspecting the above data.
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Patent Agency Ranking
公开(公告)号：US20250125712A1
公开(公告)日：2025-04-17
申请号：US18485333
申请日：2023-10-12
Inventor： YAO-WEI YANG
Abstract: A bootstrap device used for first and second transistors of a buck-boost converter includes first and second bootstrap circuits. The first bootstrap circuit generates a first bootstrap voltage, and determines, based on a change among a first switching voltage, a voltage level of a source terminal of the first transistor and the first bootstrap voltage, whether to charge according to at least one of a DC input voltage, a DC output voltage, and a second bootstrap voltage. The second bootstrap circuit generates the second bootstrap voltage, and determines, based on a change among a second switching voltage, a voltage level of a source terminal of the second transistor, and the second bootstrap voltage, whether to charge according to at least one of the DC input voltage, the DC output voltage, and the first bootstrap voltage. The bootstrap device improves charging efficiency of bootstrap capacitors.
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公开(公告)号：US12266913B2
公开(公告)日：2025-04-01
申请号：US18135935
申请日：2023-04-18
Inventor： Isaac Y. Chen
Abstract: An abnormal current protection device includes an overcurrent protector and a controller, and the overcurrent protector includes a short-circuit detection unit and an overcurrent detection unit. The short-circuit detection unit is configured to detect whether there is a short-circuit event within a period of debounce time of a protection cycle. The overcurrent detection unit is configured to detect whether there is an overcurrent event after the period of debounce time within the protection cycle. The controller is configured to disable a converter when the short-circuit event is detected, and disable a power stage when the overcurrent event is detected.
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公开(公告)号：US20240405719A1
公开(公告)日：2024-12-05
申请号：US18326034
申请日：2023-05-31
Inventor： YAO-WEI YANG
IPC: H03B5/12 , H03B5/04 , H03K3/0231
Abstract: A voltage mode controlled liner frequency modulation oscillator comprises a voltage modulation circuit, a reference current generating circuit, and an oscillating circuit. The voltage modulation circuit is configured to generate a modulation voltage according to a feedback voltage and a first reference voltage. The reference current generating circuit, coupled to the voltage modulation circuit, is configured to generate a first reference current according to the modulation voltage and a second reference voltage. The oscillating circuit, coupled to the reference current generating circuit, is configured to generate an oscillating signal with an oscillating frequency according to the first reference current, wherein the oscillating frequency varies with the modulation voltage.
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公开(公告)号：US20240322798A1
公开(公告)日：2024-09-26
申请号：US18125331
申请日：2023-03-23
Inventor： Chih-Sheng CHANG , Isaac Y. CHEN
CPC classification number: H03K3/017 , H03K3/037 , H03K19/20 , H04R3/00 , H04R29/001
Abstract: An electronic device includes a sampling circuit and a summing circuit coupled with the sampling circuit. The sampling circuit samples a pulse width of a first input pulse of a PWM input signal since a first time point on a rising edge of a clock pulse of a clock signal. The summing circuit generates a first output pulse of a PWM output signal since a second time point on a falling edge of the clock pulse. A pulse width of the first output pulse is a summation of the pulse width of the first input pulse and a pulse width of a second input pulse of the PWM input signal, and the second input pulse is the next pulse after the first input pulse.
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公开(公告)号：US12040693B2
公开(公告)日：2024-07-16
申请号：US17872024
申请日：2022-07-25
Inventor： Yao-Wei Yang
CPC classification number: H02M1/0009 , H02M3/156
Abstract: A control circuit for controlling a DC-DC converter is provided. The control circuit comprises a first sensor, second sensor, error amplifier, signal conditioning circuit, first comparison circuit, second comparison circuit, and driver circuit. The error amplifier is configured to receive a feedback voltage and a reference voltage for generating a first voltage. The signal conditioning circuit is configured to receive the first voltage for generating a second voltage and a third voltage. The first comparison circuit is configured to make a comparison based on a first sensing signal from the first sensor and the second voltage for generating a first comparison signal. The second comparison circuit is configured to make a comparison based on a second sensing signal from the second sensor and the third voltage for generating a second comparison signal. The driver circuit is for driving a power stage according to the first and second comparison signals.
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