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公开(公告)号：US4363040A
公开(公告)日：1982-12-07
申请号：US160162
申请日：1980-06-17
Applicant: Shuichi Inose
Inventor： Shuichi Inose
CPC classification number: G11B20/1419 , G11B20/1423
Abstract: There is disclosed a signal transducer for extracting only the data components from information which has been modulated by different modulation systems. More concretely, the transducer provides two kinds of clock signals with respect to the information obtained by modulating the data under the frequency-modulation system or the modified frequency-modulation system, and extracts the data components from the information in accordance with one of the two kinds of clock signals.
Abstract translation: 公开了一种用于仅从已经由不同调制系统调制的信息中提取数据分量的信号传感器。 更具体地，换能器针对通过调制频率调制系统或修改的调频系统下的数据获得的信息提供两种时钟信号，并根据两者之一从信息中提取数据分量 各种时钟信号。
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公开(公告)号：US4357707A
公开(公告)日：1982-11-02
申请号：US29065
申请日：1979-04-11
Applicant: Dale E. Delury
Inventor： Dale E. Delury
CPC classification number: G11B20/1403 , G11B20/1419 , G11B20/1423
Abstract: A digital phase lock loop system used in conjunction with a flexible disk drive controller for recovering data information from either single density or double density serially encoded data. More specifically, a phase lock system is disclosed in which data bit windows and clock bit windows are defined by a plurality of phase clock cycles. A circuit is provided for determining during which phase clock cycle a bit occurs, an adjustment being made to the duration of its corresponding bit window and thus to the initiation time of a subsequent bit window which will tend to position the window so that it will be centered about its corresponding bit. In a specific embodiment for double density encoded data, a circuit is provided whereby the subsequent bit window is positioned in accordance with the position of the current bit within its corresponding window and the position of a preceding bit within its corresponding bit window. In addition, the invention provides a circuit whereby a position of each bit within its corresponding window is counted, the net count being indicative of the number of bits appearing in the second half of their corresponding bit windows less the number of bits appearing in the first half of their corresponding bit windows. A bias phase adjustment signal is generated for altering the duration of a bit window until the net count approaches zero. This altering provides for automatic compensation of variations in disk rotation speed and/or recording speed variations.
Abstract translation: 数字锁相环系统与软盘驱动器控制器结合使用，用于从单密度或双密度串行编码数据恢复数据信息。 更具体地，公开了一种锁相系统，其中通过多个相位时钟周期来定义数据位窗口和时钟位窗口。 提供了一个电路，用于确定在哪个相位时钟周期内发生一个位，调整到其对应的位窗口的持续时间，从而进行到随后的位窗口的启动时间，这将使窗口定位， 以其对应的位为中心 在用于双密度编码数据的具体实施例中，提供电路，由此根据当前位在其对应窗口内的位置以及其对应位窗口内的前一位的位置来定位后续位窗口。 此外，本发明提供了一种电路，由此对其窗口内的每个位的位置进行计数，净计数表示出现在其对应位窗口的后半部分中的位数减去第一 它们的相应位窗口的一半。 生成偏置相位调整信号以改变位窗口的持续时间，直到净计数接近零。 该改变提供对盘旋转速度和/或记录速度变化的变化的自动补偿。
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公开(公告)号：US4345168A
公开(公告)日：1982-08-17
申请号：US136839
申请日：1980-04-03
Applicant: Alan J. Fisher
Inventor： Alan J. Fisher
CPC classification number: G11B20/1419 , G06K7/0166 , G06K7/084 , G06K7/087 , G11B15/62 , G11B20/10009 , H03K5/1532
Abstract: An electrical peak detector wherein two complementary transistors have commonly connected base leads and emitter leads, and a capacitor is connected between the collector of each transistor to a constant potential point. An input circuit is connected between the commonly connected base terminals and emitter terminals through a capacitor.
Abstract translation: 一种电峰检测器，其中两个互补晶体管具有共同连接的基极引线和发射极引线，并且电容器连接在每个晶体管的集电极到恒定电位点之间。 输入电路通过电容器连接在公共连接的基极端子和发射极端子之间。
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44.发明授权Self synchronizing clock derivation circuit for double frequency encoded digital data 失效用于双频编码数字数据的自同步时钟推导电路
公开(公告)号：US4320525A
公开(公告)日：1982-03-16
申请号：US88947
申请日：1979-10-29
Applicant: Thomas R. Woodward
Inventor： Thomas R. Woodward
CPC classification number: H04L7/0066 , G11B20/1419
Abstract: A circuit for accurately reconstructing the timing information encoded within digital waveforms of the double frequency class includes facilities for restoring the circuit to proper synchronization at start up time or after a burst of noise on an incoming waveform. The circuit first generates three delayed versions of the incoming double frequency waveform. Transitions in the incoming waveform are detected by comparing the incoming waveform with the first delayed waveform and simultaneously comparing the second and third delayed waveforms, the generated transition-event waveforms being identical but out of phase by one half of the bit cell time of the incoming waveform. The two generated transition waveforms are used to form a composite clock which is then used to toggle the state of a D-type flip-flop at one half bit cell intervals. The Q and Q outputs of the flip-flop are then gated with the first and second transition waveforms to produce first and second clocking signals, the first clocking signal commencing at each guaranteed transition in the incoming waveform, the second clocking signal commencing one-half bit cell after each guaranteed transition in the incoming waveform.In order to assure that the flip-flop is properly synchronized with the incoming waveform, the incoming waveform is additionally compared with the identical incoming waveform delayed by one-half bit cell. The signal produced and the Q output of the flip-flop are inputted to a logical NAND, and the output of the NAND is fed to the flip-flop's D-input, thus assuring that the flip-flop is synchronized with the incoming waveform.
Abstract translation: 用于精确地重建在双频率类别的数字波形内编码的定时信息的电路包括用于在启动时或在输入波形上的噪声突发之后将电路恢复到适当同步的设施。 该电路首先生成三个延迟版本的输入双频波形。 通过将输入波形与第一延迟波形进行比较并同时比较第二和第三延迟波形来检测输入波形中的转换，所产生的转换事件波形是相同的，但是异相比特输入的比特单元时间的一半 波形 两个产生的转换波形用于形成复合时钟，然后用复合时钟以半位单元间隔切换D型触发器的状态。 触发器的Q和Q输出随后被第一和第二转换波形选通，以产生第一和第二时钟信号，第一时钟信号从进入波形中的每个保证转换开始，第二时钟信号从一半开始 每个保证的输入波形转换后的位单元格。 为了确保触发器与输入波形正确同步，输入波形还与延迟了半位单元的相同输入波形进行比较。 产生的信号和触发器的Q输出被输入到逻辑“与非”，并且NAND的输出被馈送到触发器的D输入端，从而确保触发器与输入波形同步。
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公开(公告)号：US4317211A
公开(公告)日：1982-02-23
申请号：US155281
申请日：1980-06-02
Applicant: Harris A. Quesnell, Jr.
Inventor： Harris A. Quesnell, Jr.
IPC: G11B20/14 , H04L7/033 , H03K13/175
CPC classification number: H04L7/033 , G11B20/1419
Abstract: An apparatus for decoding a Manchester encoded waveform is described in wh a gating circuit responds to the mid-cell transitions in the encoded waveform to produce an enabling signal which causes a clock circuit to generate high frequency clock pulses. A programmable counter accumulates the generated clock pulses. If the counter exceeds a clock count threshold set by a multiposition switch before the beginning of the following enabling signal, it causes a storage element to sample the encoded waveform and store the sample to provide an output signal representing decoded data. A second, substantially equivalent circuit decodes timing from the encoded waveform. The multiposition switch provides the apparatus with the capability to decode encoded waveforms of varying frequency.
Abstract translation: 描述了用于解码曼彻斯特编码波形的装置，其中门控电路响应编码波形中的中间单元转换以产生使得时钟电路产生高频时钟脉冲的使能信号。 可编程计数器累加产生的时钟脉冲。 如果计数器超过由下一个使能信号开始之前由多位开关设置的时钟计数阈值，则使存储元件对编码的波形采样并存储样本以提供表示解码数据的输出信号。 第二个基本上等效的电路从编码波形解码定时。 多位开关为设备提供解码频率变化的编码波形的能力。
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Patent Agency Ranking46.发明授权
公开(公告)号：US4313206A
公开(公告)日：1982-01-26
申请号：US86268
申请日：1979-10-19
Applicant: Thomas R. Woodward
Inventor： Thomas R. Woodward
CPC classification number: H04L7/0066 , G11B20/1419
Abstract: A circuit arrangement for extracting clocking signals from double frequency encoded transition-event waveforms. The incoming waveform is fed directly into a digital delay line which generates three versions of the incoming waveform, each delayed by 1/4, 1/2 and 3/4 of the incoming waveform's bit cell time, respectively. Transitions in the incoming waveform are detected by comparing the output of the first delay line tap with the incoming waveform and simultaneously comparing the outputs of the second and third delay line taps, thus generating first and second transition waveforms that are identical but out of phase by one-half bit cell. The two generated transition waveforms are used to form a composite clock which is then used to toggle a flip-flop at one-half bit cell intervals. The true and false outputs of the flip-flop are then gated with the first and second generated transition waveforms, respectively, to produce the two desired clocking signals, the first clocking signal providing pulses commencing at the incoming waveform's guaranteed transitions, the second clocking signal providing pulses commencing one-half bit cell after the incoming waveform's guaranteed transitions.
Abstract translation: 一种用于从双频编码的转换事件波形中提取时钟信号的电路装置。 输入波形被直接馈送到数字延迟线，其产生三个版本的输入波形，分别延迟输入波形的位单元时间的1/4，1/2和3/4。 通过将第一延迟线抽头的输出与输入波形进行比较并同时比较第二和第三延迟线抽头的输出，从而产生相同但不同相的第一和第二转换波形，从而检测输入波形中的转换， 半位单元格。 两个产生的转换波形用于形成复合时钟，然后用复合时钟以半位单元间隔触发触发器。 然后分别用第一和第二产生的转换波形选通触发器的真实和错误的输出，以产生两个期望的时钟信号，第一时钟信号提供从进入的波形的保证转换开始的脉冲，第二时钟信号 在输入波形的保证转换后提供从半位单元开始的脉冲。
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47.发明授权
公开(公告)号：US4238843A
公开(公告)日：1980-12-09
申请号：US008221
申请日：1979-01-31
Applicant: Marino G. Carasso , Johannes J. Verboom , Maarten R. de Haan
Inventor： Marino G. Carasso , Johannes J. Verboom , Maarten R. de Haan
IPC: G11B20/10 , G11B7/00 , G11B7/004 , G11B7/0045 , G11B7/007 , G11B20/14 , G11B23/00 , G11B23/30 , G11B23/36 , G11C13/04
CPC classification number: G11B7/00745 , G11B20/1419 , G11B20/1423
Abstract: A disc-shaped record carrier having an information track which is divided into a plurality of sectors per track circumference. Each sector is divided into a data section, in which the data can be recorded, and a synchronizing section. This synchronizing section consists of an optically detectable relief structure and comprises an indicator portion and an address portion. The address portion contains the information about the track number and the sector number. The indicator portion serves to define the beginning of the address portion unambiguously and for this purpose has such a relief structure that the indicator signal produced after cooperation with the radiation beam has a frequency which is clearly distinguishable from signal components resulting from the address portion.
Abstract translation: 一种盘形记录载体，其具有信息轨道，每个轨道圆周被划分成多个扇区。 每个扇区被划分成可记录数据的数据部分和同步部分。 该同步部分由光学可检测的浮雕结构组成，并包括指示器部分和地址部分。 地址部分包含关于轨道号和扇区号的信息。 指示器部分用于明确地定义地址部分的开始，并且为此目的具有这样的浮雕结构，即在与辐射束协作之后产生的指示符信号具有与由地址部分产生的信号分量明显区分的频率。
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公开(公告)号：US4198663A
公开(公告)日：1980-04-15
申请号：US903695
申请日：1978-05-08
Applicant: Yasumasa Sugihara
Inventor： Yasumasa Sugihara
CPC classification number: G11B23/0007 , G11B20/1419 , G11B20/1423
Abstract: A digital signal recording system capable of a self-clocking and a peak detection. Binary data is represented by bi-level signal pulses which are spaced apart by a time interval which is a positive integral multiple of time interval of clock pulses (referred to as T.sub.0). The width of the signal pulses at their one level is a constant value less than T.sub.0 and where the time spacing between such signal pulses is greater than 2 T.sub.0, a selected number of pseudo pulses having the same pulse width as such signal pulses are inserted between the adjacent signal pulses with a time interval therefrom which is an odd multiple of T.sub.0 /2.
Abstract translation: 一种能够进行自我定时和峰值检测的数字信号记录系统。 二进制数据由双电平信号脉冲表示，间隔时间间隔是时钟脉冲的时间间隔的正整数倍（称为T0）。 信号脉冲在其一个电平上的宽度是小于T0的常数值，并且其中这种信号脉冲之间的时间间隔大于2T0，所选择数量的与这些信号脉冲具有相同脉冲宽度的伪脉冲插入在 相邻信号脉冲具有时间间隔，其为T0 / 2的奇数倍。
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公开(公告)号：US4183066A
公开(公告)日：1980-01-08
申请号：US925596
申请日：1978-07-17
Applicant: Albert L. Anderson
Inventor： Albert L. Anderson
CPC classification number: G11B20/1419 , G11B20/1423
Abstract: A method and apparatus for recording data on a rotating magnetic disk at plural density rates on different areas of the disk is disclosed. The method is particularly useful in magnetic disk recording systems in which the header or control fields of the recorded information are recorded in "single" density FM recording and the data fields of the recorded information are in "double" density modified frequency modulation (MFM) code. The technique involves changing the conventional MFM coding rules to prevent certain data patterns from appearing to the data recording system read circuitry as part of the control fields. In particular, the data pattern 011110 is encoded according to the invention as a data pattern which consists of 000000 with synchronization bits between the first and second, third and fourth, and fifth and sixth data bits. This encoding modification prevents any misinterpretation of the data field as part of a control field. The data recording circuitry used to decode the MFM information is modified from the conventional decoding circuitry so that adjacent "zero" data bits having no synchronization bit between them are decoded as adjacent "one" bits. The original data stream is thereby recovered.
Abstract translation: 公开了一种用于在盘的不同区域上以多个密度速率在旋转磁盘上记录数据的方法和装置。 该方法在磁记录系统中特别有用，其中记录的信息的标题或控制字段被记录在“单一”密度FM记录中，并且所记录信息的数据字段处于“双重”密度修改频率调制（MFM） 码。 该技术涉及改变传统的MFM编码规则，以防止某些数据模式作为控制领域的一部分出现在数据记录系统读取电路上。 特别地，数据模式011110根据本发明被编码为数据模式，该数据模式由具有第一和第二，第三和第四以及第五和第六数据位之间的同步位的000000组成。 该编码修改防止数据字段作为控制字段的一部分的任何误解。 用于对MFM信息进行解码的数据记录电路从常规解码电路进行修改，使得在它们之间没有同步位的相邻的“零”数据位被解码为相邻的“1”位。 从而恢复原始数据流。
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公开(公告)号：US4171479A
公开(公告)日：1979-10-16
申请号：US897517
申请日：1978-04-18
Applicant: Kalman Rozsa
Inventor： Kalman Rozsa
CPC classification number: G11B20/1419
Abstract: The disclosure relates to a method and device for reading data in the form of data pulses in a pulse train. The pulse train is obtained by the sensing of a flexible disc and contains, conventionally, a sequence of clock pulses which, in at least a portion of the pulse train, define mutually subsequent bit cells. These contain at most one of the data pulses. A bistable circuit is switched to its one state by the clock pulses and switched to its other state by the data pulses. The time which has elapsed after each switching of the bistable circuit is measured by means of a time circuit and the bistable circuit is switched if the elapsed time exceeds a value which is settable for each switching. A combinational circuit is provided for setting the above-mentioned level in dependence of the contents of at least the preceding bit cell.
Abstract translation: 本公开涉及一种用于以脉冲序列中的数据脉冲的形式读取数据的方法和装置。 通过感测柔性盘获得脉冲串，并且通常包含一系列时钟脉冲，其在脉冲串的至少一部分中定义相互后续的比特单元。 它们最多包含一个数据脉冲。 双稳态电路通过时钟脉冲切换到其一个状态，并通过数据脉冲切换到其它状态。 通过时间电路测量每个双稳态电路的切换之后经过的时间，如果经过时间超过每次切换可设置的值，则切换双稳态电路。 提供组合电路，用于根据至少前一位单元的内容设置上述电平。
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