公开(公告)号：US20020001965A1

公开(公告)日：2002-01-03

申请号：US08898187

申请日：1997-07-22

Inventor： LEONARD FORBES

IPC: H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  H01L021/311 ,  H01L021/302 ,  H01L021/461

CPC classification number: H01L21/32 ,  H01L21/76208 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76281 ,  Y10S148/05

Abstract: Using sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defmed on the silicon rows by LOCal Oxidation of Silicon (LOCOS).

Abstract translation: 使用亚微米技术，在硅衬底中形成绝缘体上硅（SOI）行和岛。 沟槽在硅衬底中定向蚀刻，在沟槽之间留下一排硅。 然后将氮化硅沉积在沟槽上，部分地沿着沟槽的侧面延伸。 然后使用各向同性化学蚀刻部分地削去基板中的窄排硅。 随后的氧化步骤完全底切硅排，隔离相邻的活性区域的硅排。 然后，诸如用于CMOS和DRAM的晶体管的器件形成在有源区域中，其中通过硅（LOCOS）的局部氧化将有源区域定义在硅行上。

公开(公告)号：US06287900B1

公开(公告)日：2001-09-11

申请号：US08912975

申请日：1997-08-13

Applicant: Shunpei Yamazaki ,  Jun Koyama ,  Satoshi Teramoto

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Satoshi Teramoto

IPC: H01L2100

CPC classification number: H01L21/28185 ,  H01L21/28211 ,  H01L21/2822 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76281 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/66166 ,  H01L29/66181 ,  H01L29/66772 ,  Y10S257/913

Abstract: In a MOS semiconductor device utilizing a crystalline silicon substrate, the formation of a parasitic channel is suppressed. A solution of nickel acetate is applied silicon substrate 101 to form a layer including nickel indicated by 102. Thermal oxidation is performed to form a field oxide film 103 for device separation. At this time, a halogen element is included in the atmosphere. At this step, the action of nickel suppresses the formation of defects at the interface between the oxide film 103 and a channel region 106 and in the vicinity thereof, thereby suppressing the formation of a parasitic channel. Further, as a result of the action of the halogen element, nickel is gettered into the thermal oxidation film 103.

Abstract translation: 在利用晶体硅衬底的MOS半导体器件中，抑制了寄生沟道的形成。将乙酸镍溶液施加到硅衬底101上以形成由102表示的包含镍的层。进行热氧化以形成场氧化膜 103用于设备分离。 此时，大气中含有卤素元素。 在该步骤中，镍的作用抑制在氧化膜103与沟道区域106之间及其附近的界面处的缺陷的形成，从而抑制寄生通道的形成。 此外，由于卤素元素的作用，镍被吸收到热氧化膜103中。

公开(公告)号：US06252281B1

公开(公告)日：2001-06-26

申请号：US08612456

申请日：1996-03-07

Applicant: Tadashi Yamamoto ,  Shizuo Sawada

Inventor： Tadashi Yamamoto ,  Shizuo Sawada

IPC: H01L2701

CPC classification number: H01L27/10894 ,  H01L21/76264 ,  H01L21/76281 ,  H01L27/10811 ,  H01L27/10873 ,  H01L27/1203

Abstract: Silicon oxide layers are provided in a substrate. That part of the silicon oxide layer which is located in a memory cell section MC has a thickness. That part of the silicon oxide layer which is located in a peripheral circuit section PC has a thickness, which is less than the thickness. The memory cell section MC has transistors, each having a source region and a drain region which contact the silicon oxide layer. The peripheral circuit section PC has transistors, each having a source region and a drain region which are spaced apart from the silicon oxide layer. The transistors of the peripheral circuit section PC are provided in well regions. A back-gate bias is applied to the transistors of the peripheral circuit section PC through impurity layers.

Abstract translation: 氧化硅层设置在基板中。 位于存储单元部分MC中的部分氧化硅层具有厚度。 位于外围电路部分PC中的部分氧化硅层的厚度小于厚度。 存储单元部MC具有各自具有与氧化硅层接触的源极区域和漏极区域的晶体管。 外围电路部分PC具有各自具有与氧化硅层间隔开的源极区域和漏极区域的晶体管。 外围电路部分PC的晶体管设置在阱区中。 背栅极偏置通过杂质层施加到外围电路部分PC的晶体管。

公开(公告)号：US06214693B1

公开(公告)日：2001-04-10

申请号：US09404801

申请日：1999-09-24

Applicant: Hiroshi Komatsu

Inventor： Hiroshi Komatsu

IPC: H01L2176

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/78648

Abstract: A process for the production of a semiconductor device comprising the steps of; (a) forming a patterned mask layer on a surface of a semiconductor substrate, (b) etching the semiconductor substrate using the mask layer as an etching mask, to form a step between a portion of the semiconductor substrate covered with the mask layer and an etched portion of the semiconductor substrate, (c) forming an insulating film on the entire surface, and then planarizing the insulating film to cover the etched portion of the semiconductor substrate with the insulating film, (d) removing the mask layer, then, forming a first gate insulating film on an exposed surface of the semiconductor substrate, then forming a first gate electrode on the first gate insulating film, and at the same time, forming a first word line extending from the first gate electrode on the insulating film, (e) forming an interlayer on the entire surface, and bonding the semiconductor substrate and a supporting substrate to each other through the interlayer, (f) grinding and polishing the semiconductor substrate from its rear surface to expose a bottom surface of the insulating film and to leave a semiconductive layer which is the semiconductor substrate remaining after the polishing, surrounded by the insulating film, and (g) forming a second gate insulating film on an exposed surface of the semiconductive layer, then forming a second gate electrode on the second gate insulating film, and at the same time, forming a second word line extending from the second gate electrode on the insulating film.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤： （a）在半导体衬底的表面上形成图案化的掩模层，（b）使用掩模层作为蚀刻掩模蚀刻半导体衬底，以在被掩模层覆盖的半导体衬底的一部分和 蚀刻部分，（c）在整个表面上形成绝缘膜，然后用绝缘膜平面化绝缘膜以覆盖半导体衬底的蚀刻部分，（d）去除掩模层，然后形成 在所述半导体衬底的暴露表面上的第一栅极绝缘膜，然后在所述第一栅极绝缘膜上形成第一栅电极，并且同时形成从所述绝缘膜上的所述第一栅电极延伸的第一字线（ e）在整个表面上形成中间层，并通过中间层将半导体衬底和支撑衬底彼此接合，（f）研磨和抛光半导体衬底 从其后表面露出绝缘膜的底表面，并且留下半导体层，半导体衬底是抛光之后残留的半导体衬底，被绝缘膜包围，并且（g）在暴露表面上形成第二栅极绝缘膜 然后在第二栅极绝缘膜上形成第二栅电极，同时形成从绝缘膜上的第二栅电极延伸的第二字线。

公开(公告)号：US6130457A

公开(公告)日：2000-10-10

申请号：US192125

申请日：1998-11-13

Applicant: Sun-il Yu ,  Woo-tag Kang

Inventor： Sun-il Yu ,  Woo-tag Kang

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L29/78603 ,  H01L29/78612 ,  H01L21/76272 ,  H01L21/76281 ,  Y10S438/977

Abstract: Methods of forming semiconductor-on-insulator substrates include the steps of forming a underlying semiconductor layer to electrically interconnect a plurality of SOI active regions and thereby prevent one or more of the active regions from "floating" relative to the other active regions. The reduction of floating body effects (FBE) improves the I-V characteristics of SOI devices including SOI MOSFETs. A method is provided which includes the steps of forming a second electrically insulating layer having a plurality of first openings therein, on a first face of a first semiconductor substrate. A first semiconductor layer is then formed on the second electrically insulating layer so that direct electrical connections are made between the first semiconductor layer and the first semiconductor substrate. A first electrically insulating layer is then formed on the first semiconductor layer. This first electrically insulating layer is then planarized and bonded to a second semiconductor substrate. The composite intermediate structure is then inverted and followed by the step of planarizing a second face of the first semiconductor substrate to define a second semiconductor layer. A plurality of spaced semiconductor active regions are then defined in the second semiconductor layer by using field oxide isolation techniques to consume the entire thickness of the second semiconductor layer at predetermined spaced locations. This step essentially isolates the active regions from each other, however, these active regions do not "float" because they are electrically connected to each other indirectly through the underlying first semiconductor layer.

Abstract translation: 形成绝缘体上半导体衬底的方法包括以下步骤：形成下面的半导体层以电连接多个SOI有源区，从而防止一个或多个有源区相对于其它有源区“漂浮”。 浮体效应（FBE）的降低提高了包括SOI MOSFET在内的SOI器件的I-V特性。 提供了一种方法，其包括在第一半导体衬底的第一面上形成其中具有多个第一开口的第二电绝缘层的步骤。 然后在第二电绝缘层上形成第一半导体层，使得在第一半导体层和第一半导体衬底之间形成直接电连接。 然后在第一半导体层上形成第一电绝缘层。 然后将该第一电绝缘层平坦化并结合到第二半导体衬底。 然后将复合中间结构反转，随后平面化第一半导体衬底的第二面以限定第二半导体层的步骤。 然后通过使用场氧化物隔离技术在第二半导体层中限定多个间隔的半导体有源区，以在预定的间隔位置消耗第二半导体层的整个厚度。 该步骤基本上将活性区域彼此隔离，然而，这些活性区域不会“浮动”，因为它们通过下面的第一半导体层间接地彼此电连接。

公开(公告)号：US6117711A

公开(公告)日：2000-09-12

申请号：US33560

申请日：1998-03-02

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/762 ,  H01L21/8238

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  H01L21/76264 ,  H01L21/823878 ,  H01L21/76267 ,  H01L21/76281 ,  Y10S977/937

Abstract: The present invention includes forming field oxide (FOX) isolations on a substrate. A pad oxide layer is then formed on the substrate. An ion implantation is carried out to dope dopants into the substrate by using FOX as a hard mask. Thus, a buried oxygen amorphized region is formed in the substrate. Subsequently, a high temperature thermal anneal is performed to convert the oxygen amorphized region into an buried oxide layer, thereby forming localized Si islands between the substrate and the buried oxide layer. A further thermal oxidation is used to narrow the thickness of the localized Si islands, thereby forming nanometer Si wires. Then, a further ultra thin gate oxide layer is regrow on the nanometer Si wires. Then, CMOS transistors are formed on the substrate.

Abstract translation: 本发明包括在基底上形成场氧化物（FOX）隔离物。 然后在衬底上形成衬垫氧化物层。 通过使用FOX作为硬掩模，进行离子注入以将掺杂剂掺杂到衬底中。 因此，在衬底中形成掩埋的氧非晶形区域。 随后，进行高温热退火以将氧非晶化区域转换为掩埋氧化物层，从而在衬底和掩埋氧化物层之间形成局部Si岛。 使用进一步的热氧化来缩小局部Si岛的厚度，从而形成纳米Si线。 然后，另外的超薄栅极氧化层在纳米Si导线上再生长。 然后，在基板上形成CMOS晶体管。

公开(公告)号：US6100159A

公开(公告)日：2000-08-08

申请号：US965339

申请日：1997-11-06

Applicant: Zoran Krivokapic

Inventor： Zoran Krivokapic

IPC: H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/76

CPC classification number: H01L29/66651 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/76297 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835 ,  H01L21/76281

Abstract: The present invention provides a fabrication process for fabricating a semiconductor integrated circuit device on a silicon substrate having an active device region isolated from the underlying substrate similar to a silicon on insulator(soi) substrate structure. The quasi-soi structure provides an inexpensive semiconductor integrated circuit device having a reduced floating body effect. The process for fabricating the substrate for use in fabricating the quasi-soi semiconductor device includes the steps of providing a silicon substrate member, fabricating at least one passivation layer consisting of silicon nitride over the silicon substrate member and protecting an underlying substrate surface region for subsequent fabrication of isolation trench regions, fabricating the isolation trench regions by etching portions of the passivation layer and portions of the substrate surface region forming an epitaxial silicon growing region. The process further includes the steps of fabricating the epitaxial silicon layer on the epitaxial silicon growing region and over the oxide isolation trenches, fabricating an MOS gate structure region including a silicon dioxide layer grown over the epitaxial silicon layer, and a polysilicon layer deposited over said silicon dioxide layer. The MOS gate structure is further surrounded by a spacer region under which is formed the devices channel region and salicidated source and drain regions for the quasi-soi semiconductor device. The source and drain regions are an implanted dopant material extending from the channel region to form an electrical path to a respective one of said isolation trench regions forming a capacitance junction.

Abstract translation: 本发明提供一种用于在硅衬底上制造半导体集成电路器件的制造工艺，其具有与绝缘体上硅衬底结构类似的从底层衬底隔离的有源器件区域。 准Soi结构提供了具有减少的浮体效应的便宜的半导体集成电路器件。 用于制造用于制备准半导体器件的衬底的工艺包括以下步骤：提供硅衬底构件，在硅衬底构件上制造由氮化硅组成的至少一个钝化层，并保护下面的衬底表面区域用于随后的 制造隔离沟槽区域，通过蚀刻钝化层的部分和形成外延硅生长区的衬底表面区域的部分来制造隔离沟槽区域。 该工艺还包括在外延硅生长区和氧化物隔离沟槽上方制造外延硅层的步骤，制造包括在外延硅层上生长的二氧化硅层的MOS栅极结构区域和沉积在所述外延硅层上的多晶硅层 二氧化硅层。 MOS栅极结构进一步被间隔区围绕，在该间隔区域形成准半导体器件的器件沟道区域和水银源极和漏极区域。 源区和漏区是从沟道区延伸的注入的掺杂剂材料，以形成形成电容结的所述隔离沟槽区中的相应一个的电路。

公开(公告)号：US6060751A

公开(公告)日：2000-05-09

申请号：US676965

申请日：1996-07-08

Applicant: Mamoru Terauchi ,  Manabu Kamikokuryou

Inventor： Mamoru Terauchi ,  Manabu Kamikokuryou

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L21/76264 ,  H01L21/76281

Abstract: A semiconductor device comprises a composite substrate comprising a semiconductor substrate and a semiconductor layer on said semiconductor substrate with a dielectric layer interposed therebetween; a plurality of element regions formed in the semiconductor layer and each having formed a field effect transistor including a source region and a drain region of a first conduction type; and an impurity-diffused region of a second conduction type which is formed directly under an element isolating film isolating respective elements. The impurity-diffused region having the opposite conduction type and formed under the element separating film restrain formation of parasitic transistors and prevent a decrease in threshold value.The semiconductor device can be fabricated by preparing a SOI substrate; making a mask on the composite substrate and having an aperture on a location to be used for isolating elements; using the mask to form both an element isolating insulation film and first conduction type impurity-diffused regions in locations corresponding to outer marginal portions of elements to be made; and forming second conduction type impurity-diffused regions on the semiconductor layer as sources of drains of the elements.

Abstract translation: 半导体器件包括复合衬底，该复合衬底包括半导体衬底和位于所述半导体衬底上的介电层之间的半导体层; 形成在所述半导体层中并且各自形成有包括第一导电类型的源极区域和漏极区域的场效应晶体管的多个元件区域; 以及直接形成在隔离各元件的元件隔离膜下面的第二导电类型的杂质扩散区域。 具有相反导电类型且形成在元件分离膜下方的杂质扩散区域抑制寄生晶体管的形成并且防止阈值的降低。 可以通过制备SOI衬底来制造半导体器件; 在复合衬底上制作掩模，并且在用于隔离元件的位置处具有孔; 使用掩模在与要制造的元件的外边缘部分相对应的位置中形成元件隔离绝缘膜和第一导电类型杂质扩散区域; 以及在所述半导体层上形成第二导电型杂质扩散区域作为所述元件的漏极源。

公开(公告)号：US5981359A

公开(公告)日：1999-11-09

申请号：US954613

申请日：1997-10-20

Applicant: Hideaki Onishi

Inventor： Hideaki Onishi

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76281

Abstract: Disclosed is a method of manufacturing a semiconductor device having a reliable element isolation insulating film on an SOI substrate having an SOI layer. That is, the step of forming a semiconductor device on an SOI substrate includes the steps of sequentially depositing a silicon oxide film and an insulating film resistant to oxidation on the surface of the SOI layer of the SOI substrate to form a stacked film, etching the stacked film into a predetermined pattern shape to expose the SOI layer, selectively forming a thin silicon layer on the exposed SOI layer, and selectively thermally oxidizing the thin silicon layer and the exposed SOI layer by using the stacked film as a thermal oxidization mask. In the thermal oxidization step, all the thin silicon layer and the exposed SOI layer are thermally oxidized to be converted into an element isolation insulating film, and the element isolation insulating film is formed in contact with a buried oxide film below the region. Since the thin silicon layer is selectively formed in advance on the SOI layer to be converted into the element isolation insulating film, the element isolation insulating film is made thick. Even after the process of manufacturing the semiconductor device, a sufficiently thick element isolation insulating film is ensured.

Abstract translation: 公开了一种在具有SOI层的SOI衬底上制造具有可靠元件隔离绝缘膜的半导体器件的方法。 也就是说，在SOI衬底上形成半导体器件的步骤包括以下步骤：在SOI衬底的SOI层的表面上依次沉积耐氧化的氧化硅膜和绝缘膜以形成层叠膜，蚀刻 层叠成预定图案形状以露出SOI层，在暴露的SOI层上选择性地形成薄硅层，并且通过使用堆叠膜作为热氧化掩模来选择性地热氧化薄硅层和暴露的SOI层。 在热氧化步骤中，所有的薄硅层和暴露的SOI层都被热氧化以转化为元件隔离绝缘膜，并且元件隔离绝缘膜形成为与该区域下方的掩埋氧化膜接触。 由于预先在SOI层上选择性地形成薄硅层以转换为元件隔离绝缘膜，所以元件隔离绝缘膜变厚。 即使在制造半导体器件的过程之后，确保了足够厚的元件隔离绝缘膜。

公开(公告)号：US5854120A

公开(公告)日：1998-12-29

申请号：US769031

申请日：1996-12-17

Applicant: Yuichi Urano ,  Masato Nishizawa ,  Yoshiyuki Sakai ,  Naoki Ito ,  Shinichi Hashimoto

Inventor： Yuichi Urano ,  Masato Nishizawa ,  Yoshiyuki Sakai ,  Naoki Ito ,  Shinichi Hashimoto

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L27/08 ,  H01L27/12

CPC classification number: H01L21/7624 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76286 ,  Y10S438/92

Abstract: A polysilicon film is deposited in a trench formed in a silicon element substrate. The polysilicon film in the trench and on the silicon element substrate is anisotropically etched, so that the film remains on the side wall of the trench. The polysilicon film on the side wall is oxidized to obtain an insulating film, which buries the trench. At the same time, an oxidized film is formed on the surface of the silicon element substrate to complete a trench-mold separation area.