公开(公告)号：US20120306012A1

公开(公告)日：2012-12-06

申请号：US13532507

申请日：2012-06-25

申请人： Vijay Parthasarathy ,  Sujit Banerjee

发明人： Vijay Parthasarathy ,  Sujit Banerjee

IPC分类号： H01L27/088

CPC分类号： H01L29/772 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/7835

摘要： In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET.

摘要翻译： 在一个实施例中，功率集成电路器件包括形成在高电阻率衬底上的主横向高电压场效应晶体管（HVFET）和相邻定位的横向感测FET。 感测电阻器形成在设置在HVFET和感测FET之间的衬底区域中的阱区中。 寄生衬底电阻器形成为与HVFET的源极区域和感测FET之间的感测电阻器并联电连接。 两个晶体管器件共享共同的漏极和栅电极。 当主横向HVFET和感测FET处于导通状态时，在与流过横向HVFET的第一电流成比例的第二源极金属层处产生电压电位。

公开(公告)号：US20120223371A1

公开(公告)日：2012-09-06

申请号：US13470861

申请日：2012-05-14

申请人： Gil Shalev ,  Amihood Doron ,  Ariel Cohen

发明人： Gil Shalev ,  Amihood Doron ,  Ariel Cohen

IPC分类号： G01N27/414 ,  H01L21/66

CPC分类号： H01L29/772 ,  G01N33/5438 ,  H01L29/42316 ,  H01L29/7831 ,  Y10T436/11

摘要： A multiple-gate field-effect transistor includes a fluid in a top gate, two lateral gates, and a bottom gate. The multiple-gate field-effect transistor also includes a patterned depletion zone and a virtual depletion zone that has a lesser width than the patterned depletion zone. The virtual depletion zone width creates a virtual semiconductor nanowire that is lesser in width than the patterned depletion zone.

摘要翻译： 多栅极场效应晶体管包括顶栅中的流体，两个横向栅极和底栅极。 多栅极场效应晶体管还包括图案化耗尽区和具有比图案化耗尽区更小的宽度的虚拟耗尽区。 虚拟耗尽区宽度产生的虚拟半导体纳米线的宽度小于图案化的耗尽区。

公开(公告)号：US08241913B2

公开(公告)日：2012-08-14

申请号：US13216005

申请日：2011-08-23

申请人： Gil Shalev ,  Amihood Doron ,  Ariel Cohen

发明人： Gil Shalev ,  Amihood Doron ,  Ariel Cohen

IPC分类号： G01N15/06 ,  G01N33/00 ,  G01N33/48

CPC分类号： H01L29/772 ,  G01N33/5438 ,  H01L29/42316 ,  H01L29/7831 ,  Y10T436/11

摘要： A multiple-gate field-effect transistor includes a fluid in a top gate, two lateral gates, and a bottom gate. The multiple-gate field-effect transistor also includes a patterned depletion zone and a virtual depletion zone that has a lesser width than the patterned depletion zone. The virtual depletion zone width creates a virtual semiconductor nanowire that is lesser in width than the patterned depletion zone.

摘要翻译： 多栅极场效应晶体管包括顶栅中的流体，两个横向栅极和底栅极。 多栅极场效应晶体管还包括图案化耗尽区和具有比图案化耗尽区更小的宽度的虚拟耗尽区。 虚拟耗尽区宽度产生的虚拟半导体纳米线的宽度小于图案化的耗尽区。

公开(公告)号：US08227841B2

公开(公告)日：2012-07-24

申请号：US12431670

申请日：2009-04-28

申请人： Gilberto Curatola

发明人： Gilberto Curatola

IPC分类号： H01L29/76

CPC分类号： H01L29/772 ,  H01L29/66356 ,  H01L29/66477 ,  H01L29/7391 ,  H01L29/78 ,  Y10S257/90

摘要： An impact ionization MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by a silicon-germanium intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region.

摘要翻译： 冲击电离MOSFET形成为从栅极偏移到垂直于器件结构而不是水平放置的源/漏区之一。 半导体器件包括具有第一掺杂水平的第一源极/漏极区域; 具有第二掺杂水平并且与第一源极/漏极区相反的掺杂剂类型的第二源极/漏极区域，第一和第二源极/漏极区域被硅 - 锗中间区域横向隔开，所述硅 - 锗中间区域的掺杂水平小于 第一和第二掺杂水平; 与所述中间区域电绝缘并设置在所述中间区域上的栅电极，所述第一和第二源极/漏极区域与所述栅电极横向对准; 其中形成与中间区域的边界的第一源极/漏极区域的整个部分与中间区域的顶部垂直分离。

公开(公告)号：US08221884B2

公开(公告)日：2012-07-17

申请号：US13168279

申请日：2011-06-24

申请人： Walt A. DeHeer

发明人： Walt A. DeHeer

IPC分类号： B32B9/00

CPC分类号： H01L21/8213 ,  H01L21/0405 ,  H01L21/0445 ,  H01L29/16 ,  H01L29/1606 ,  H01L29/772 ,  H01L29/7781 ,  Y10S977/742 ,  Y10T428/30 ,  Y10T428/31504

摘要： In a method of making graphite devices, a thin-film graphitic layer disposed against a preselected face of a substrate is created on the preselected face of the substrate. A preselected pattern is generated on the thin-film graphitic layer. At least one functionalizing molecule is attached to a portion of the graphitic layer. The molecule is capable of interacting with π bands in the graphitic layer.

摘要翻译： 在制造石墨器件的方法中，在衬底的预选面上产生靠着衬底的预选面设置的薄膜石墨层。 在薄膜石墨层上产生预选图案。 至少一个官能化分子连接到石墨层的一部分。 该分子能够与pgr 石墨层中的带。

公开(公告)号：US20120091470A1

公开(公告)日：2012-04-19

申请号：US13334720

申请日：2011-12-22

申请人： Michael A. Briere

发明人： Michael A. Briere

IPC分类号： H01L29/161 ,  H01L21/20 ,  H01L29/20

CPC分类号： H01L29/778 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/51 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/772 ,  H01L29/7787 ,  H01L29/803

摘要： A III-nitride semiconductor device which includes a charged floating gate electrode.

摘要翻译： 一种III族氮化物半导体器件，其包括带电的浮置栅电极。

公开(公告)号：US20120081977A1

公开(公告)日：2012-04-05

申请号：US13245220

申请日：2011-09-26

申请人： Yuniarto WIDJAJA ,  Zvi Or-Bach

发明人： Yuniarto WIDJAJA ,  Zvi Or-Bach

IPC分类号： G11C7/00

CPC分类号： H01L27/10802 ,  G11C7/22 ,  G11C11/04 ,  G11C11/39 ,  G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/0018 ,  G11C2211/4016 ,  H01L23/528 ,  H01L29/1095 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/772 ,  H01L29/7841 ,  H01L29/7881

摘要： A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.

公开(公告)号：US20120074469A1

公开(公告)日：2012-03-29

申请号：US12888828

申请日：2010-09-23

申请人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

发明人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

IPC分类号： H01L29/80 ,  G06F17/50 ,  H01L21/337

CPC分类号： H01L29/772 ,  G06F17/50 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/66901 ,  H01L29/808

摘要： A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce Ron. A related method and design structure are also disclosed.

摘要翻译： 提供了一种用于集成电路（IC）芯片的结栅场效应晶体管（JFET），其包括源极区，漏极区，下栅极和沟道，其中绝缘浅沟槽隔离（STI）区域从 源区域的上表面的内边缘到漏极区域的上表面的内边缘，而没有有意掺杂的区域，例如上栅极，与源极/漏极区域之间的IC芯片的上表面共面 。 此外，可以包括设置在STI区域的一部分下方的不对称的准掩埋的上栅极，但不在靠近漏极区域的STI区域的一部分下方延伸。 本发明的实施例还包括在源极区域下提供注入层以减少Ron。 还公开了相关的方法和设计结构。

公开(公告)号：US20110304317A1

公开(公告)日：2011-12-15

申请号：US13216005

申请日：2011-08-23

申请人： Gil Shalev ,  Amihood Doron ,  Ariel Cohen

发明人： Gil Shalev ,  Amihood Doron ,  Ariel Cohen

IPC分类号： G01R19/00

CPC分类号： H01L29/772 ,  G01N33/5438 ,  H01L29/42316 ,  H01L29/7831 ,  Y10T436/11

摘要： A multiple-gate field-effect transistor includes a fluid in a top gate, two lateral gates, and a bottom gate. The multiple-gate field-effect transistor also includes a patterned depletion zone and a virtual depletion zone that has a lesser width than the patterned depletion zone. The virtual depletion zone width creates a virtual semiconductor nanowire that is lesser in width than the patterned depletion zone.

摘要翻译： 多栅极场效应晶体管包括顶栅中的流体，两个横向栅极和底栅极。 多栅极场效应晶体管还包括图案化耗尽区和具有比图案化耗尽区更小的宽度的虚拟耗尽区。 虚拟耗尽区宽度产生的虚拟半导体纳米线的宽度小于图案化的耗尽区。

公开(公告)号：US08013398B2

公开(公告)日：2011-09-06

申请号：US12056909

申请日：2008-03-27

申请人： Shinji Mori ,  Tsutomu Sato ,  Koji Matsuo

发明人： Shinji Mori ,  Tsutomu Sato ,  Koji Matsuo

IPC分类号： H01L29/78

CPC分类号： H01L29/772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof.

摘要翻译： 半导体器件包括具有Si沟道的第一pMISFET区，具有Si沟道的第二pMISFET区和具有Si沟道的nMISFET区。 将第一压缩应变施加到Si沟道的第一SiGe层嵌入并形成在第一pMISFET区域中以夹持其Si沟道，并且将施加与第一压缩应变不同的第二压缩应变的第二SiGe层嵌入并形成 在第二pMISFET区域夹持其Si通道。