Stacked composite device including a group III-V transistor and a group IV vertical transistor
    1.
    发明授权
    Stacked composite device including a group III-V transistor and a group IV vertical transistor 有权
    堆叠复合器件包括III-V族晶体管和IV族垂直晶体管

    公开(公告)号:US09343440B2

    公开(公告)日:2016-05-17

    申请号:US13434412

    申请日:2012-03-29

    IPC分类号: H01L25/07 H03K17/567

    摘要: In one implementation, a stacked composite device comprises a group IV vertical transistor and a group III-V transistor stacked over the group IV vertical transistor. A drain of the group IV vertical transistor is in contact with a source of the group III-V transistor, a source of the group IV vertical transistor is coupled to a gate of the group III-V transistor to provide a composite source on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on a top side of the stacked composite device. A gate of the group IV vertical transistor provides a composite gate on the top side of the stacked composite device.

    摘要翻译: 在一个实施方案中,堆叠的复合器件包括堆叠在IV族垂直晶体管上的IV族垂直晶体管和III-V族晶体管。 IV族垂直晶体管的漏极与III-V晶体管的源极接触,IV族垂直晶体管的源极耦合到III-V族晶体管的栅极,以在底部提供复合源极 并且III-V族晶体管的漏极在堆叠的复合器件的顶侧提供复合漏极。 IV组垂直晶体管的栅极在堆叠的复合器件的顶侧提供复合栅极。

    Composite semiconductor device with a SOI substrate having an integrated diode
    2.
    发明授权
    Composite semiconductor device with a SOI substrate having an integrated diode 有权
    具有集成二极管的SOI衬底的复合半导体器件

    公开(公告)号:US09281388B2

    公开(公告)日:2016-03-08

    申请号:US13544829

    申请日:2012-07-09

    申请人: Michael A. Briere

    发明人: Michael A. Briere

    摘要: There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a semiconductor on insulator (SOI) substrate including a diode and an insulator layer. The composite semiconductor device also includes a transition body formed over the diode, and a transistor formed over the transition body. The diode is connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two.

    摘要翻译: 这里公开了复合半导体器件的各种实现方式。 在一个实施方案中,这种复合半导体器件包括包括二极管和绝缘体层的绝缘体上半导体(SOI)衬底。 复合半导体器件还包括形成在二极管上的跃迁体和形成在过渡体上的晶体管。 二极管通过半导体通孔,外部电连接器或两者的组合在晶体管两端连接。

    Semiconductor package with integrated passives and method for fabricating same
    3.
    发明授权
    Semiconductor package with integrated passives and method for fabricating same 有权
    具有集成无源的半导体封装及其制造方法

    公开(公告)号:US09159679B2

    公开(公告)日:2015-10-13

    申请号:US12584420

    申请日:2009-09-03

    申请人: Michael A. Briere

    发明人: Michael A. Briere

    IPC分类号: H01L23/64 H01L23/522

    摘要: According to one disclosed embodiment, a semiconductor package for integrated passives and a semiconductor device comprises a high permeability structure formed over a surface of the semiconductor package and surrounding a contact body of the semiconductor package, the contact body being connected to an output of the semiconductor device. The contact body can be, for example, a solder bump. The high permeability structure causes a substantial increase in inductance of the contact body so as to form an increased inductance inductor coupled to the output of the semiconductor device. In one embodiment, the semiconductor package further comprises a blanket insulator formed over the high permeability structure, and a capacitor stack formed over the blanket insulator. In one embodiment, the semiconductor device comprises a group III-V power semiconductor device.

    摘要翻译: 根据一个公开的实施例,用于集成无源的半导体封装和半导体器件包括形成在半导体封装的表面上并围绕半导体封装的接触体的高磁导率结构,该接触体连接到半导体的输出端 设备。 接触体可以是例如焊料凸块。 高导磁率结构导致接触体的电感的显着增加,从而形成耦合到半导体器件的输出的增加的电感电感器。 在一个实施例中,半导体封装还包括形成在高导磁率结构上的覆盖绝缘体,以及形成在覆盖绝缘体上的电容器堆叠。 在一个实施例中,半导体器件包括III-V族功率半导体器件。

    P type III-nitride materials and formation thereof
    6.
    发明授权
    P type III-nitride materials and formation thereof 有权
    P型III族氮化物材料及其形成

    公开(公告)号:US08729561B1

    公开(公告)日:2014-05-20

    申请号:US13455023

    申请日:2012-04-24

    申请人: Michael A. Briere

    发明人: Michael A. Briere

    摘要: In one implementation, a method of forming a P type III-nitride material includes forming a getter material over a III-nitride material, the III-nitride material having residual complexes formed from P type dopants and carrier gas impurities. The method further includes gettering at least some of the carrier gas impurities, from at least some of the residual complexes, into the getter material to form the P type III-nitride material. In some implementations, the carrier gas impurities include hydrogen and the getter material includes at least partially titanium. An overlying material can be formed on the getter material prior to gettering at least some of the carrier gas impurities.

    摘要翻译: 在一个实施方案中,形成P型III族氮化物材料的方法包括在III族氮化物材料上形成吸气材料,III族氮化物材料具有由P型掺杂剂和载气杂质形成的残余络合物。 该方法还包括将至少一些载气杂质从至少一些残留配合物吸入吸气材料中以形成P型III族氮化物材料。 在一些实施方案中,载气杂质包括氢,吸气材料至少部分包括钛。 在吸入至少一些载气杂质之前,可以在吸气剂材料上形成覆盖材料。

    Nested Composite Switch
    8.
    发明申请
    Nested Composite Switch 有权
    嵌套复合开关

    公开(公告)号:US20130015905A1

    公开(公告)日:2013-01-17

    申请号:US13542194

    申请日:2012-07-05

    申请人: Michael A. Briere

    发明人: Michael A. Briere

    IPC分类号: H03K17/687 H03K17/56

    摘要: There are disclosed herein various implementations of nested composite switches. In one implementation, a nested composite switch includes a normally ON primary transistor coupled to a composite switch. The composite switch includes a low voltage (LV) transistor cascoded with an intermediate transistor having a breakdown voltage greater than the LV transistor and less than the normally ON primary transistor. In one implementation, the normally on primary transistor may be a group III-V transistor and the LV transistor may be an LV group IV transistor.

    摘要翻译: 这里公开了嵌套复合交换机的各种实施方式。 在一个实施方案中,嵌套复合开关包括耦合到复合开关的正常的初级晶体管。 复合开关包括与具有大于LV晶体管的击穿电压并小于正常导通初级晶体管的中间晶体管级联的低电压(LV)晶体管。 在一个实施方案中,正常导通的主晶体管可以是III-V族晶体管,并且LV晶体管可以是LV组IV晶体管。

    High Voltage Rectifier and Switching Circuits
    10.
    发明申请
    High Voltage Rectifier and Switching Circuits 有权
    高压整流器和开关电路

    公开(公告)号:US20120235209A1

    公开(公告)日:2012-09-20

    申请号:US13288500

    申请日:2011-11-03

    IPC分类号: H01L29/778 H01L27/088

    摘要: According to one exemplary embodiment, a rectifier circuit includes a diode. A first depletion-mode transistor is connected to a cathode of the diode. Also, at least one second depletion-mode transistor is in parallel with the first depletion-mode transistor and is configured to supply a pre-determined current range to a cathode of the diode. A pinch off voltage of the at least one second depletion-mode transistor can be more negative than a pinch off voltage of the first depletion-mode transistor and the at least one second depletion-mode transistor can be configured to supply the pre-determined current range while the first depletion-mode transistor is OFF. Also, the pre-determined current range can be greater than a leakage current of the first depletion-mode transistor.

    摘要翻译: 根据一个示例性实施例,整流器电路包括二极管。 第一耗尽型晶体管连接到二极管的阴极。 此外,至少一个第二耗尽型晶体管与第一耗尽型晶体管并联并且被配置为向二极管的阴极提供预定电流范围。 至少一个第二耗尽型晶体管的截止电压可以比第一耗尽型晶体管的夹断电压更负,并且至少一个第二耗尽型晶体管可以被配置为提供预定电流 而第一耗尽型晶体管为OFF时。 此外,预定电流范围可以大于第一耗尽型晶体管的漏电流。