公开(公告)号：US20120155165A1

公开(公告)日：2012-06-21

申请号：US12970744

申请日：2010-12-16

申请人： Dieter BIMBERG ,  Martin Geller ,  Andreas Marent ,  Tobias Nowozin

发明人： Dieter BIMBERG ,  Martin Geller ,  Andreas Marent ,  Tobias Nowozin

IPC分类号： H01L29/68 ,  G11C11/34 ,  H01L29/778 ,  H01L29/66

CPC分类号： B82Y10/00 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/803

摘要： An embodiment of the invention relates to a memory comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers, wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers, the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1.15 eV or higher, and provides an energy state density of at least three energy states per 1000 nm3, all said at least three energy states being located in an energy band of 50 meV or less.

摘要翻译： 本发明的一个实施例涉及包含应变双异质结构的存储器，其具有夹在两个外半导体层之间的内半导体层，其中内半导体层的晶格常数与外半导体层的晶格常数不同， 所述双异质结构中的晶格应变导致在所述内半导体层内部形成至少一个量子点，所述至少一个量子点能够在其中存储电荷载流子，并且其中由于晶格应变，所述至少一个 量子点具有1.15eV或更高的发射势垒，并且提供每1000nm 3至少三个能量状态的能态状态密度，所有所述至少三个能态位于50meV或更小的能带内。

公开(公告)号：US08084785B2

公开(公告)日：2011-12-27

申请号：US11857113

申请日：2007-09-18

申请人： Michael A. Briere

发明人： Michael A. Briere

IPC分类号： H01L29/739

CPC分类号： H01L29/778 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/51 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/772 ,  H01L29/7787 ,  H01L29/803

摘要： A III-nitride semiconductor device which includes a charged floating gate electrode.

摘要翻译： 一种III族氮化物半导体器件，其包括带电的浮置栅电极。

公开(公告)号：US20110147708A1

公开(公告)日：2011-06-23

申请号：US12643848

申请日：2009-12-21

申请人： Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Niloy Mukherjee

发明人： Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Niloy Mukherjee

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7783 ,  B82Y10/00 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7785 ,  H01L29/7848 ,  H01L29/802 ,  H01L29/803

摘要： Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了用于增加集成电路器件的载流子注入速度的结构和技术。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一阻挡膜，耦合到第一阻挡膜的量子阱沟道，该量子阱沟道包括具有第一带隙能量的第一材料和耦合到 将移动电荷载流子发射到量子阱沟道中，源结构包括具有第二带隙能量的第二材料，其中第二带隙能量大于第一带隙能量。 可以描述和/或要求保护其他实施例。

公开(公告)号：US07622763B2

公开(公告)日：2009-11-24

申请号：US10565624

申请日：2004-07-28

申请人： Jun Suda ,  Hiroyuki Matsunami

发明人： Jun Suda ,  Hiroyuki Matsunami

IPC分类号： H01L29/792

CPC分类号： H01L21/28158 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/511 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7883 ,  H01L29/802 ,  H01L29/803

摘要： A field effect transistor comprises a SiC substrate 1, a source 3a and a drain 3b formed on the surface of the SiC substrate 1, an insulating structure comprising an AlN layer 5 formed in contact with the SiC surface and having a thickness of one molecule-layer or greater, and a SiO2 layer formed thereon, and a gate electrode 15 formed on the insulation structure. Leakage current can be controlled while the state of interface with SiC is maintained in a good condition.

摘要翻译： 场效应晶体管包括SiC衬底1，形成在SiC衬底1的表面上的源极3a和漏极3b，绝缘结构，其包括与SiC表面接触形成的AlN层5， 层或更大，以及形成在其上的SiO 2层，以及形成在绝缘结构上的栅电极15。 可以控制漏电流，同时与SiC的界面状态保持良好状态。

公开(公告)号：US20080087917A1

公开(公告)日：2008-04-17

申请号：US11857113

申请日：2007-09-18

申请人： Michael Briere

发明人： Michael Briere

IPC分类号： H01L29/739 ,  H01L21/336

CPC分类号： H01L29/778 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/51 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/772 ,  H01L29/7787 ,  H01L29/803

摘要： A III-nitride semiconductor device which includes a charged floating gate electrode.

摘要翻译： 一种III族氮化物半导体器件，其包括带电的浮置栅电极。

公开(公告)号：US6080995A

公开(公告)日：2000-06-27

申请号：US89389

申请日：1998-06-03

申请人： Kazumasa Nomoto

发明人： Kazumasa Nomoto

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L29/80

CPC分类号： H01L29/803

摘要： A quantum device functioning as a memory device is provided for allowing high-speed writing and erasing of data with a low gate voltage. A source electrode and a drain electrode are formed on a substrate. A gate electrode is formed between the source and drain electrodes. Between the substrate and the gate electrode, a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer and a third barrier layer are stacked to form coupled quantum well layer. The thickness of each of the first and second barrier layers allows electron tunneling. The thickness of the third barrier layer does not allow electron tunneling. The energy level of the first quantum well layer is higher than the Fermi level of a conduction layer. The energy level of the second quantum well layer is lower than the energy level of the first quantum well layer. With an application of voltage to the gate electrode, a transition of electrons takes place by means of tunneling through the first quantum well layer to the second quantum well layer and the electrons are accumulated therein.

摘要翻译： 提供用作存储器件的量子器件，用于允许以低栅极电压高速写入和擦除数据。 在基板上形成源电极和漏电极。 在电极和漏电极之间形成栅电极。 在基板和栅电极之间，层叠第一阻挡层，第一量子阱层，第二势垒层，第二量子阱层和第三势垒层，形成耦合的量子阱层。 每个第一和第二阻挡层的厚度允许电子隧穿。 第三阻挡层的厚度不允许电子隧穿。 第一量子阱层的能级高于导电层的费米能级。 第二量子阱层的能级低于第一量子阱层的能级。 通过向栅电极施加电压，通过穿过第一量子阱层到第二量子阱层并且电子在其中积累而发生电子的转变。

公开(公告)号：US5432356A

公开(公告)日：1995-07-11

申请号：US222634

申请日：1994-04-04

申请人： Kenichi Imamura

发明人： Kenichi Imamura

IPC分类号： H01L29/205 ,  H01L29/267 ,  H01L29/80 ,  H01L29/861

CPC分类号： H01L29/205 ,  H01L29/267 ,  H01L29/803 ,  H01L29/8616

摘要： A semiconductor memory device comprises a non-doped thick barrier layer formed on the semiconductor substrate, an impurity doped floating conducting layer formed on the thick barrier layer, a thin barrier layer formed on the floating conducting layer and having an asymmetric barrier whose barrier height is higher on the side of the floating conducting layer, a channel layer formed on the thin barrier layer, and a first electrode and a second electrode formed on the channel layer. A write bias voltage which makes a potential of the second electrode higher than that of the first electrode is applied so as to inject electrons from the first electrode to the floating conducting layer through the thin barrier layer, thereby writing information in the floating conducting layer. A read bias voltage lower than the write bias voltage is applied between the first and the second electrodes, and the information stored in the floating conducting layer is read based on whether or not a current flows in the channel layer.

摘要翻译： 半导体存储器件包括形成在半导体衬底上的非掺杂厚势垒层，形成在厚势垒层上的杂质掺杂浮动导电层，形成在浮动导电层上的薄势垒层，并且具有阻挡高度为 在浮动导电层的一侧较高，形成在薄阻挡层上的沟道层，以及形成在沟道层上的第一电极和第二电极。 施加使第二电极的电位高于第一电极的写偏置电压，以便通过薄势垒层将电子从第一电极注入到浮动导电层，从而在浮动导电层中写入信息。 在第一和第二电极之间施加低于写入偏置电压的读取偏置电压，并且基于电流是否流过沟道层来读取存储在浮置导电层中的信息。