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    LDPC decoding apparatus, decoding method and program
    41.
    发明授权
    LDPC decoding apparatus, decoding method and program 有权
    LDPC解码装置，解码方法和程序

    公开(公告)号：US08281205B2

    公开(公告)日：2012-10-02

    申请号：US12252470

    申请日：2008-10-16

    申请人： Takashi Yokokawa

    发明人： Takashi Yokokawa

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1168 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/1165 ,  H03M13/616 ,  H03M13/6508 ,  H03M13/6577

    摘要： Disclosed herein is a decoding apparatus for decoding an LDPC code, the decoding apparatus including: a message computation section configured to carry out a process of decoding received values, where notation F denotes a non-unity measure of the integer P, and outputting F messages; a shift section configured to carry out F×F cyclic shift operations on the F messages and output F messages; a storage section configured to store the F messages and allow the stored F messages to be read out or to store F received values cited above and allow the stored F received values to be read out; and a control section configured to control an operation to supply a unit composed of the F received values to the message computation section by carrying out at least a column rearrangement process or a process equivalent to the column rearrangement process on the received values.

    摘要翻译： 这里公开了一种解码LDPC码的解码装置，该解码装置包括：消息计算部，被配置为执行对接收值进行解码的处理，其中，F表示整数P的非一致性度量，并输出F个消息 ; 移位部，被配置为对所述F个消息进行F×F循环移位操作，并输出F个消息; 存储部，其被配置为存储所述F个消息，并且允许所存储的F个消息被读出或存储上述引用的F个接收值，并且允许读取所存储的F个接收值; 以及控制部，被配置为通过对接收到的值执行至少一个列重排处理或与该列重排处理相当的处理来控制将由F个接收值组成的单元提供给消息计算部的操作。

    CHECK MATRIX CREATION DEVICE, CHECK MATRIX CREATION METHOD, CHECK MATRIX CREATION PROGRAM, TRANSMITTER, RECEIVER, AND COMMUNICATION SYSTEM
    44.
    发明申请
    CHECK MATRIX CREATION DEVICE, CHECK MATRIX CREATION METHOD, CHECK MATRIX CREATION PROGRAM, TRANSMITTER, RECEIVER, AND COMMUNICATION SYSTEM 审中-公开
    检查矩阵创建设备，检查矩阵创建方法，检查矩阵创建程序，发送器，接收器和通信系统

    公开(公告)号：US20110154151A1

    公开(公告)日：2011-06-23

    申请号：US13002342

    申请日：2009-06-26

    申请人： Wataru Matsumoto ,  Hideo Yoshida

    发明人： Wataru Matsumoto ,  Hideo Yoshida

    IPC分类号： H03M13/11 ,  G06F11/10

    CPC分类号： H03M13/116 ,  H03M13/1168

    摘要： A check matrix creation device includes a circulant permutation matrix setting unit 12 for preparing a plurality of circulant permutation matrices each having an inner diameter of six or larger, and a quasi-cyclic matrix creation unit 13 for arranging the plurality of circulant permutation matrices prepared by the circulant permutation matrix setting unit 12 both in a row direction and in a column direction to create a quasi-cyclic matrix.

    摘要翻译： 校验矩阵创建装置包括：循环置换矩阵设置单元12，用于准备多个具有六个或更大内径的循环置换矩阵;以及准循环矩阵创建单元13，用于布置由 循环置换矩阵设置单元12在行方向和列方向上以产生准循环矩阵。

    Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation
    45.
    发明授权
    Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation 有权
    用于使用多级置换执行低密度奇偶校验（LDPC）码操作的方法和装置

    公开(公告)号：US07966542B2

    公开(公告)日：2011-06-21

    申请号：US11674147

    申请日：2007-02-13

    申请人： Tom Richardson

    发明人： Tom Richardson

    IPC分类号： H03M13/00

    CPC分类号： H03M13/6508 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/1168 ,  H03M13/118 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/6505 ,  H03M13/6516

    摘要： Methods and apparatus of the present invention are used to implement a communications system wherein different devices using the same LDPC code are implemented using different levels of parallelism. The use of a novel class of LDPC codes makes such differences in parallelism possible. Use of a factorable permuter in various embodiments of the invention make LDPC devices with different levels of parallelism in the encoder and decoder relatively easy to implement when using the codes in the class of LDPC codes discussed herein. The factorable permuter is implemented as a controllable multi-stage switching device which performs none, one, or multiple sequential reordering operations on a Z element vector passed between memory and a Z element vector processor, with the switching one individual vectors being controlled in accordance with the graph structure of the code being implemented.

    摘要翻译： 本发明的方法和装置用于实现通信系统，其中使用不同级别的并行性来实现使用相同LDPC码的不同设备。 使用新颖的LDPC码类使得并行性的这种差异成为可能。 在本发明的各种实施例中使用因子式置换器在编码器和解码器中使用具有不同级别的并行性的LDPC装置在使用本文所讨论的LDPC码类中的代码时相对容易实现。 因子置换器被实现为可控多级切换装置，其对在存储器和Z元素向量处理器之间传递的Z元素向量执行一次，一次或多次顺序重排序操作，其中切换一个单独的向量根据 正在执行的代码的图形结构。

    ERROR CORRECTION CODING METHOD AND DEVICE
    46.
    发明申请
    ERROR CORRECTION CODING METHOD AND DEVICE 有权
    错误校正编码方法和设备

    公开(公告)号：US20090187810A1

    公开(公告)日：2009-07-23

    申请号：US12300412

    申请日：2007-04-25

    申请人： Norifumi Kamiya

    发明人： Norifumi Kamiya

    IPC分类号： H03M13/15 ,  G06F17/10 ,  G06F11/10

    CPC分类号： H03M13/11 ,  G11B20/18 ,  H03M13/1151 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1168 ,  H03M13/611 ,  H03M13/617 ,  H03M13/6561

    摘要： An error correction coding method using a low-density parity-check code includes: dividing an information bit sequence to be processed for error correction coding, into (m−r) pieces of first blocks each comprising a bit sequence having a length n and r pieces of second blocks comprising respective bit sequences having lengths k1, k2, . . . , kr; a first arithmetic operation for performing polynomial multiplication on the (m−r) pieces of first blocks, and outputting r pieces of bit sequences having a length n; and a second arithmetic operation for performing a polynomial division and a polynomial multiplication on the r pieces of second blocks and r pieces of operation results of the first arithmetic operation, and outputting a bit sequence including redundant bit sequences having respective lengths n−k1, n−k2, . . . , n−kr.

    摘要翻译： 使用低密度奇偶校验码的纠错编码方法包括：将要进行纠错编码处理的信息比特序列划分为（mr）个第一块，每个第一块包括长度为n的比特序列和r个 第二块包括具有长度k1，k2，...的各个比特序列。 。 。 ，kr; 用于对（m-r）个第一块进行多项式乘法并输出具有长度为n的r个比特序列的第一算术运算; 以及第二算术运算，用于对第一运算结果的r个第二块和r个运算结果执行多项式除法和多项式乘法，并输出包括具有各自长度n-k1，n的冗余位序列的比特序列 -k2， 。 。 ，n-kr。

    Decoder and decoding method for decoding low-density parity-check codes with parity check matrix
    48.
    发明授权
    Decoder and decoding method for decoding low-density parity-check codes with parity check matrix 有权
    用奇偶校验矩阵解码低密度奇偶校验码的解码和解码方法

    公开(公告)号：US07500168B2

    公开(公告)日：2009-03-03

    申请号：US11168329

    申请日：2005-06-29

    申请人： Kenji Yoshida

    发明人： Kenji Yoshida

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1168 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116

    摘要： In an LDPC-code decoder, bit-processing units are provided, respectively, for the 1st to Mth rows of the parity-check matrix that is formed of (r×s) permuted matrices having respective arrays of (m×m). Each of bit-processing units sequentially updates bit information corresponding to column positions included in the respective rows of the parity-check matrix, a bit at each of the column positions being set to “1”.Parity-processing units update parity information corresponding to row positions in columns of each column block of the parity-check matrix, whenever the bit-processing units have finished bit update computation for m column positions in each column block, a bit at each row position being set to “1”.The bit-processing units starts next bit update computation after the parity-processing units finish parity update computation for m columns of the first column block of the parity-check matrix.

    摘要翻译： 在LDPC码解码器中，针对由具有（m×m）的各自的阵列的（rxs）置换矩阵形成的奇偶校验矩阵的第1〜第M行分别提供比特处理单位。 每个位处理单元顺序地更新与奇偶校验矩阵的相应行中包括的列位置相对应的位信息，每个列位置处的位被设置为“1”。微处理单元更新对应于 每当位处理单元完成每列列中的m列位置的位更新计算时，每行位置的位被设置为“1”，位的位列位于奇偶校验矩阵的每个列块的列中 在奇偶校验处理单元完成奇偶校验矩阵的第一列块的m列的奇偶校验更新计算之后，处理单元开始下一位更新计算。

    Strengthening parity check bit protection for array-like LDPC codes
    49.
    发明申请
    Strengthening parity check bit protection for array-like LDPC codes 有权
    加强阵列状LDPC码的奇偶校验位保护

    公开(公告)号：US20080235559A1

    公开(公告)日：2008-09-25

    申请号：US11726310

    申请日：2007-03-20

    申请人： Sizhen Yang

    发明人： Sizhen Yang

    IPC分类号： H03M13/11

    CPC分类号： H03M13/1168 ,  H03M13/1111 ,  H03M13/118 ,  H03M13/2957 ,  H03M13/6331

    摘要： An LDPC parity check matrix originated using an array code provides more protection against errors for parity bits 1 through 1-p, which can, during decoding, allow faster convergence to a higher LLR value for those bits as well as higher overall reliability of other parity check bits. The present parity check matrix provides an upper triangular sub-matrix (H1) for the parity check bits, where column weights for parity bits 1 through p-1 can be greater than 1. Aspects include encoders to encode user bits using the parity check matrix, decoders to decode based on the parity check matrix, systems comprising encoders and/or decoders, encoder and decoder methods; as well as computer readable media comprising programs for implementing such methods.

    摘要翻译： 使用阵列码发起的LDPC奇偶校验矩阵为奇偶校验位1到1-p提供了更多的针对错误的保护，其可以在解码期间允许更快地收敛到这些比特的更高的LLR值以及更高的其他奇偶校验的可靠性 检查位。 当前的奇偶校验矩阵为奇偶校验位提供上三角子矩阵（H 1> 1），其中奇偶校验位1到p-1的列权重可以大于1.方面包括编码器 使用奇偶校验矩阵对用户比特进行编码，解码器基于奇偶校验矩阵进行解码，包括编码器和/或解码器的系统，编码器和解码器方法; 以及包括用于实现这种方法的程序的计算机可读介质。