公开(公告)号：US20240403524A1

公开(公告)日：2024-12-05

申请号：US18779321

申请日：2024-07-22

Applicant: Celera, Inc.

Inventor： Calum MacRae ,  Jim LoCascio ,  Richard Philpott

IPC: G06F30/327 ,  G06F30/31 ,  G06F30/347 ,  G06F30/367 ,  G06F30/373 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F111/12

Abstract: Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

公开(公告)号：US11941337B1

公开(公告)日：2024-03-26

申请号：US17390882

申请日：2021-07-31

Applicant: Keysight Technologies, Inc.

Inventor： Jianjun Xu ,  David E. Root

IPC: G06F30/30 ,  G06F30/27 ,  G06F30/38 ,  G06F30/39 ,  G06N3/08

CPC classification number: G06F30/38 ,  G06F30/27 ,  G06F30/39 ,  G06N3/08

Abstract: A method of modeling a nonlinear component includes providing a physical model for modeling a characteristic of the nonlinear component defined by a physical expression having a physical nonlinear function depending on variables and parameters of the nonlinear component; determining performance data for the characteristic; extracting global parameter values for the parameters based on the performance data; extracting local parameter values for the selected parameter, while keeping fixed the extracted global parameter values for the remaining parameters, based on the performance data corresponding to the characteristic using the physical expression; training an ANN function from the extracted local parameter values for the selected parameter depending on a variable; and determining a hybrid model for modeling the characteristic of the nonlinear component defined by a modified physical expression including the physical nonlinear function, the remaining parameters, and the trained ANN function depending on the variable in place of the selected parameter.

公开(公告)号：US11797742B1

公开(公告)日：2023-10-24

申请号：US17559901

申请日：2021-12-22

Applicant: Synopsys, Inc.

Inventor： Diganchal Chakraborty ,  Jiri Prevratil ,  Harsh Chilwal ,  Shreedhar Ramachandra ,  Prasenjit Biswas

IPC: G06F30/38 ,  G06F30/398 ,  G06F30/323 ,  G06F30/3308 ,  G06F119/06

CPC classification number: G06F30/38 ,  G06F30/323 ,  G06F30/3308 ,  G06F30/398 ,  G06F2119/06

Abstract: A method includes: receiving a representation of a mixed-signal integrated circuit design including an analog circuit portion and a digital circuit portion including a plurality of descriptions of a power supply, the descriptions including a power supply network description and a register transfer level (RTL) hardware description language (HDL) description; determining a mismatch between the power supply network description and the HDL description of the power supply; generating a value converter to convert a voltage value associated with the power supply between the power supply network description and the HDL description; and converting, by a processor, between the power supply network description and the HDL description during runtime using the value converter to synchronize the power supply network description and the HDL description of the power supply responsive to the mismatch.

公开(公告)号：US20230334207A1

公开(公告)日：2023-10-19

申请号：US18314000

申请日：2023-05-08

Applicant: Celera, Inc.

Inventor： Calum MacRae ,  John Mason ,  Karen Mason

IPC: G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  G06F30/367 ,  G06F30/38 ,  G06F30/31

CPC classification number: G06F30/327 ,  G06F30/31 ,  G06F30/367 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F2111/12

Abstract: Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

公开(公告)号：US11768987B2

公开(公告)日：2023-09-26

申请号：US16836945

申请日：2020-04-01

Applicant: NXP USA, Inc.

Inventor： Sandeep Jain ,  Kirk Taylor ,  Vivek Sharma ,  Arpita Agarwal

IPC: G06F30/38 ,  G06F9/30 ,  G06F7/58 ,  G06F30/398

CPC classification number: G06F30/38 ,  G06F7/58 ,  G06F9/30021 ,  G06F30/398

Abstract: A system to facilitate communication of a critical signal between functional circuitries of a system-on-chip utilizes a dynamic pattern to securely communicate the critical signal. The system includes selection and comparison circuits. The selection circuit is configured to select and output a set of dynamic pattern bits or a set of fixed reference bits, based on a logic state of the critical signal that is received from one functional circuitry. The comparison circuit is configured to output an output signal based on the set of dynamic pattern bits, and a set of intermediate bits that is derived from the set of dynamic pattern bits or the set of fixed reference bits. The output signal is provided to the other functional circuitry when a logic state of the output signal matches the logic state of the critical signal, thereby securely communicating the critical signal to the other functional circuitry.

公开(公告)号：US20230281367A1

公开(公告)日：2023-09-07

申请号：US18314004

申请日：2023-05-08

Applicant: Celera, Inc.

Inventor： Calum MacRae ,  Jim LoCascio ,  Karen Mason ,  John Mason ,  Richard Philpott ,  Muhammed Abid Hussain

IPC: G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  G06F30/367 ,  G06F30/38 ,  G06F30/31

CPC classification number: G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  G06F30/367 ,  G06F30/38 ,  G06F30/31 ,  G06F2111/12

Abstract: Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

公开(公告)号：US11694007B2

公开(公告)日：2023-07-04

申请号：US17507504

申请日：2021-10-21

Applicant: Celera, Inc.

Inventor： Karen Mason ,  John Mason

IPC: G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  G06F30/367 ,  G06F30/38 ,  G06F30/31 ,  G06F111/12

CPC classification number: G06F30/327 ,  G06F30/31 ,  G06F30/367 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F2111/12

Abstract: Automated circuit and layout generation is disclosed. Various embodiments may include a computer system and/or method for generating a circuit layout comprising specifying a circuit schematic to be converted to a circuit layout, receiving a layout script associated with the circuit schematic, the layout script configured to position a plurality of layout instances generated from the circuit schematic, converting the circuit schematic into the plurality of layout instances; and positioning the plurality of layout instances based on the layout script to produce the circuit layout. A circuit may be produced by fabricating a circuit using the layout.

公开(公告)号：US11656872B2

公开(公告)日：2023-05-23

申请号：US16914025

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Martin Langhammer

IPC: G06F9/30 ,  G06N20/00 ,  G06F30/343 ,  G06F30/34 ,  G06F30/38 ,  G06F7/50 ,  G06F7/523 ,  H03K19/17748 ,  H03M7/24 ,  G06F7/556 ,  H03K19/177 ,  G06F7/483

CPC classification number: G06F9/30101 ,  G06F7/50 ,  G06F7/523 ,  G06F7/556 ,  G06F9/30105 ,  G06F30/34 ,  G06F30/343 ,  G06F30/38 ,  G06N20/00 ,  H03K19/177 ,  H03K19/17748 ,  H03M7/24 ,  G06F7/483

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. In a first mode of operation, the first and second pluralities of values are received via a first portion of the plurality of inputs. In a second mode of operation, the first plurality of values is received via a second portion of the plurality of inputs, and the second plurality of values is received via the first portion of the plurality of inputs. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

公开(公告)号：US11550983B2

公开(公告)日：2023-01-10

申请号：US16682807

申请日：2019-11-13

Applicant: Commissariat à l'Energie Atomique et aux Energies Alternatives

Inventor： Sylvain Lespinats

IPC: G06F30/30 ,  G06F30/367 ,  H02S50/10 ,  G06F30/38 ,  G06F119/06

Abstract: A method for determining an electrical model of a string of photovoltaic modules from a characteristic I(V) of the string includes detecting a first linear zone and a second linear zone of the characteristic I(V); initialising the parameters of a non-by-pass electrical model corresponding to a first operating condition, called a non-by-pass condition; optimising the parameters of the non-by-pass electrical model from a reference characteristic I(Vref) equal to I(V), determining the parameters of the electrical model corresponding to a second operating condition, called a by-pass condition, in order to obtain a by-pass electrical model from the characteristic determining, from the characteristic I(V) the best model among the non-by-pass model and the by-pass model.

公开(公告)号：US11520584B2

公开(公告)日：2022-12-06

申请号：US16914098

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Dongdong Chen ,  Jason R. Bergendahl

IPC: G06F9/30 ,  G06N20/00 ,  G06F30/343 ,  G06F30/34 ,  G06F30/38 ,  G06F7/50 ,  G06F7/523 ,  H03K19/17748 ,  H03M7/24 ,  G06F7/556 ,  H03K19/177 ,  G06F7/483

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.