公开(公告)号：US06380590B1

公开(公告)日：2002-04-30

申请号：US09792139

申请日：2001-02-22

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2701

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/78684

Abstract: A semiconductor-on-insulator (SOI) chip. The SOI chip includes a substrate; a buried oxide (BOX) layer disposed on the substrate; an active layer disposed on the BOX layer, the active layer having a first area made from silicon and a second area made from silicon-germanium; a first device fabricated in the first area of the active layer and having a silicon channel and a first threshold voltage; and a second device fabricated in the second area of the active layer and having a silicon-germanium channel and a second threshold voltage differing from the first threshold voltage. Also discussed are alternative forms of the SOI chip and methods of making the SOI chip.

Abstract translation: 绝缘体上半导体（SOI）芯片。 SOI芯片包括基板; 设置在基板上的掩埋氧化物（BOX）层; 设置在所述BOX层上的有源层，所述有源层具有由硅制成的第一区域和由硅 - 锗制成的第二区域; 在有源层的第一区域中制造并具有硅沟道和第一阈值电压的第一器件; 以及在所述有源层的第二区域中制造并具有硅 - 锗沟道和与所述第一阈值电压不同的第二阈值电压的第二器件。 还讨论了SOI芯片的替代形式和制造SOI芯片的方法。

公开(公告)号：US06380038B1

公开(公告)日：2002-04-30

申请号：US09703512

申请日：2000-10-30

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/42376 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/4983 ,  H01L29/66484 ,  H01L29/66643 ,  H01L29/7831

Abstract: A method of fabricating an integrated circuit provides a transistor having less susceptibility to short channel effects. The transistor utilizes a U-shaped gate conductor and a main gate conductor. The U-shaped gate conductor can provide electrically induced source/drain extensions. The transistor can be a PMOS or NMOS transistor.

Abstract translation: 制造集成电路的方法提供了对短沟道效应具有较小敏感性的晶体管。 晶体管采用U形栅极导体和主栅极导体。 U形栅极导体可以提供电感应的源极/漏极延伸。 晶体管可以是PMOS或NMOS晶体管。

公开(公告)号：US06372589B1

公开(公告)日：2002-04-16

申请号：US09552050

申请日：2000-04-19

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L21/2251 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method of fabricating an integrated circuit (IC) with source and drain extension regions. Advantageously, the source and drain extension regions are formed without damage related to integrated circuit implant techniques. Damage is avoided by using solid phase doping to form extension regions. Generally, a doped material is provided adjacent to a transistor gate structure and the IC is annealed. During the annealing process, dopants from the doped material diffuse into the semiconductor substrate to form the source and drain extension regions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs).

Abstract translation: 一种制造具有源极和漏极延伸区域的集成电路（IC）的方法。 有利地，源极和漏极延伸区域形成为与集成电路注入技术相关的损害。 通过使用固相掺杂形成延伸区域可以避免损伤。 通常，掺杂材料被设置成与晶体管栅极结构相邻并且IC被退火。 在退火过程中，来自掺杂材料的掺杂剂扩散到半导体衬底中以形成源极和漏极延伸区域。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06368982B1

公开(公告)日：2002-04-09

申请号：US09713391

申请日：2000-11-15

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2100

CPC classification number: H01L21/28123 ,  H01L21/32139

Abstract: In a method for patterning a target material on a semiconductor substrate, a first hardmask material is deposited on the target material and a second hardmask material is deposited on the first hardmask material. The first hardmask material is different from the target material, and the second hardmask material is different from the first hardmask material. A patterned structure of a patterning material such a photoresist material is formed on the second hardmask material. Any exposed region of the second hardmask material is etched such that a second hardmask structure is formed from the second hardmask material remaining under the patterned structure. The etching reactant for etching the second hardmask material to form the second hardmask structure substantially does not etch the first hardmask material. The second hardmask structure is trimmed to reduce the length at each side of the second hardmask structure. Any exposed region of the first hardmask material is etched using a second etching reactant such that a first hardmask structure is formed from the first hardmask material remaining under the second hardmask structure. The second etching reactant substantially does not etch the second hardmask structure and the target material. The first hardmask structure is trimmed with a second trimming reactant to reduce the length at each side of first second hardmask structure. Any exposed region of the target material is etched using a third etching reactant such that a target structure is formed from the target material remaining under the first hardmask structure.

Abstract translation: 在用于在半导体衬底上图案化目标材料的方法中，将第一硬掩模材料沉积在目标材料上，并且将第二硬掩模材料沉积在第一硬掩模材料上。 第一硬掩模材料与目标材料不同，第二硬掩模材料与第一硬掩模材料不同。 在第二硬掩模材料上形成诸如光致抗蚀剂材料的图案形成材料的图案化结构。 蚀刻第二硬掩模材料的任何暴露区域，使得第二硬掩模结构由残留在图案化结构下的第二硬掩模材料形成。 用于蚀刻第二硬掩模材料以形成第二硬掩模结构的蚀刻反应物基本上不蚀刻第一硬掩模材料。 修整第二个硬掩模结构以减少第二个硬掩模结构的每一侧的长度。 使用第二蚀刻反应物蚀刻第一硬掩模材料的任何暴露区域，使得第一硬掩模结构由保留在第二硬掩模结构下的第一硬掩模材料形成。 第二蚀刻反应物基本上不蚀刻第二硬掩模结构和目标材料。 第一硬掩模结构用第二修剪反应物修剪以减小第一硬硬掩模结构的每一侧的长度。 使用第三蚀刻反应物蚀刻目标材料的任何曝光区域，使得目标结构由保留在第一硬掩模结构下的目标材料形成。

公开(公告)号：US06348387B1

公开(公告)日：2002-02-19

申请号：US09612771

申请日：2000-07-10

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/665 ,  H01L29/1083 ,  H01L29/4983 ,  H01L29/7831 ,  H01L29/7833

Abstract: For fabricating a field effect transistor within an active device area of a semiconductor substrate, a gate dielectric is formed on the active device area of the semiconductor substrate, and a gate structure is formed on the gate dielectric with the gate structure being comprised of a first conductive material. A drain spacer comprised of a second conductive material is formed on a first sidewall of the gate structure, and a first liner dielectric is formed between the drain spacer and the first sidewall of the gate structure and between the drain spacer and the semiconductor substrate. A source spacer comprised of the second conductive material is formed on a second sidewall of the gate structure, and a second liner dielectric is formed between the source spacer and the second sidewall of the gate structure and between the source spacer and the semiconductor substrate. Application of at least a drain threshold voltage on the drain spacer with respect to the semiconductor substrate induces charge accumulation in the semiconductor substrate under the first liner dielectric to form a drain extension of the field effect transistor. Similarly, application of at least a source threshold voltage on the source spacer with respect to the semiconductor substrate induces charge accumulation in the semiconductor substrate under the second liner dielectric to form a source extension of the field effect transistor. In this manner, the drain and source extensions of the field effect transistor are electrically induced to have a depth that is shallow regardless of thermal processes used for fabrication of the integrated circuit having the field effect transistor.

Abstract translation: 为了在半导体衬底的有源器件区域内制造场效应晶体管，在半导体衬底的有源器件区域上形成栅极电介质，并且栅极结构形成在栅极电介质上，栅极结构由第一 导电材料。 在栅极结构的第一侧壁上形成由第二导电材料构成的漏极间隔，并且在漏极间隔物和栅极结构的第一侧壁之间以及在漏极间隔物和半导体衬底之间形成第一衬垫电介质。 由栅极结构的第二侧壁上形成由第二导电材料构成的源间隔物，在栅极结构的源间隔物和第二侧壁之间以及源间隔物与半导体衬底之间形成第二衬垫电介质。 在漏极间隔物上至少施加相对于半导体衬底的漏极阈值电压，在第一衬底电介质下方的半导体衬底中引起电荷积累，以形成场效应晶体管的漏极延伸。 类似地，相对于半导体衬底施加至少源极间隔物上的源极阈值电压，在第二衬底电介质下方的半导体衬底中引起电荷积累，以形成场效应晶体管的源极延伸。 以这种方式，无论用于制造具有场效应晶体管的集成电路的热处理如何，场效应晶体管的漏极和源极延伸都被电感应为具有浅的深度。

公开(公告)号：US06326291B1

公开(公告)日：2001-12-04

申请号：US09808839

申请日：2001-03-15

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L213205

CPC classification number: H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/66545

Abstract: For fabricating a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the MOSFET has a drain region, a source region, and a channel region, and the MOSFET initially has a gate comprised of a capping layer on a polysilicon gate structure disposed on a gate dielectric. A drain silicide is formed in the drain region, and a source silicide is formed in the source region. The drain and source silicides have a first silicide thickness. A first dielectric layer is conformally deposited over the drain region, the source region, and the gate and is polished down until the capping layer of the gate is exposed such that the capping layer and the first dielectric layer are substantially level. A top portion of the first dielectric layer is etched away until sidewalls at a top portion of the polysilicon gate structure are exposed. The capping layer on the polysilicon gate structure of the gate is etched away such that the top of the polysilicon gate structure is exposed. A silicidation metal is deposited to cover the top and the sidewalls of the top portion of the polysilicon gate structure that is exposed. A silicidation anneal is performed with the silicidation metal and the top portion of the polysilicon gate structure to form a gate silicide having a second silicide thickness on top of the polysilicon gate structure. Because the gate silicide is formed from the top and the sidewalls of the top portion of the polysilicon gate structure, the gate silicide has a width that is larger than the width of the polysilicon gate structure. In addition, the gate silicide is formed in a separate step from the step for forming the drain silicide and the source silicide such that the gate silicide may have a larger thickness and be comprised of different metal silicide material from that of the drain silicide and the source silicide.

Abstract translation: 为了制造MOSFET（金属氧化物半导体场效应晶体管），MOSFET具有漏极区域，源极区域和沟道区域，并且MOSFET最初具有由位于栅极上的多晶硅栅极结构上的覆盖层构成的栅极 电介质。 在漏极区域形成漏极硅化物，在源极区域形成源极硅化物。 漏极和源极硅化物具有第一硅化物厚度。 第一电介质层被共形沉积在漏极区域，源极区域和栅极上并被抛光，直到栅极的覆盖层被暴露，使得覆盖层和第一介电层基本上是水平的。 第一电介质层的顶部被蚀刻掉，直到多晶硅栅极结构的顶部的侧壁露出。 栅极的多晶硅栅极结构上的覆盖层被蚀刻掉，使得多晶硅栅极结构的顶部被暴露。 沉积硅化金属以覆盖暴露的多晶硅栅极结构的顶部的顶部和侧壁。 用硅化金属和多晶硅栅极结构的顶部进行硅化退火以在多晶硅栅极结构的顶部上形成具有第二硅化物厚度的栅极硅化物。 因为栅极硅化物由多晶硅栅极结构的顶部的顶部和侧壁形成，栅极硅化物的宽度大于多晶硅栅极结构的宽度。 此外，栅极硅化物在与用于形成漏极硅化物和源极硅化物的步骤分开的步骤中形成，使得栅极硅化物可以具有更大的厚度并且由漏极硅化物的不同的金属硅化物材料构成，并且 源硅化物。

公开(公告)号：US06313505B2

公开(公告)日：2001-11-06

申请号：US09145785

申请日：1998-09-02

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L27088

CPC classification number: H01L29/665 ,  H01L21/26506 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/90

Abstract: A method for making a ULSI MOSFET chip includes forming the gate of a transistor on a silicon substrate, covering the gate with a SiON protective layer, and then implanting a pre-amorphization high dose Si or Ge implant into the substrate. Next, dopant is pre-implanted into the substrate to promote subsequent formation of source and drain extensions, with the SiON layer protecting the gate from the pre-amorphization high dose Si or Ge and from the dopant. Undoped polysilicon and polygermanium is then deposited onto the substrate adjacent the gate at relatively low temperatures (600° C.) to establish elevated source and drain regions without excessively thermally stressing the chip. The SiON layer is removed from the gate, and the gate and elevated source and drain regions are implanted with dopant, followed by rapid thermal annealing to form the source and drain extensions in the substrate below the gate. The gate and elevated source and drain regions are then silicidized.

Abstract translation: 制造ULSI MOSFET芯片的方法包括在硅衬底上形成晶体管的栅极，用SiON保护层覆盖栅极，然后将预非晶化高剂量Si或Ge注入物注入到衬底中。 接下来，将掺杂剂预先植入衬底中以促进随后形成源极和漏极扩展，SiON层保护栅极免受预非晶化高剂量Si或Ge和掺杂剂的侵蚀。 然后在较低温度（600℃）下将未掺杂的多晶硅和多晶锗沉积在与栅极相邻的衬底上，以建立升高的源极和漏极区域，而不会使芯片过度热应力。 从栅极去除SiON层，并且用掺杂剂注入栅极和升高的源极和漏极区域，随后快速热退火以在栅极下方的衬底中形成源极和漏极延伸。 然后将栅极和升高的源极和漏极区域硅化。

公开(公告)号：US06300182B1

公开(公告)日：2001-10-09

申请号：US09734449

申请日：2000-12-11

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L218238

CPC classification number: H01L29/78654 ,  H01L21/26586 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785

Abstract: For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a pillar of semiconductor material is formed on a layer of buried insulating material. The pillar has a top surface, a left side surface, a right side surface, a front side surface, and a back side surface, and the pillar has a width and a length. A dielectric structure comprised of a hardmask dielectric material is formed on the top surface of the pillar. A first gate dielectric is formed on the left side surface of the pillar, and a second gate dielectric is formed on the right side surface of the pillar, along a gate length of the length of the pillar. A gate electrode material is deposited on the dielectric structure and on the first gate dielectric and the second gate dielectric to surround the pillar at the top surface and the left and right side surfaces of the pillar for the gate length of the pillar. A first gate dopant is implanted at an angle directed toward the gate electrode material on the left side surface of the pillar such that the first gate dopant is not implanted into the gate electrode material on the right side surface of the pillar. In addition, a second gate dopant is implanted at an angle directed toward the gate electrode material on the right side surface of the pillar such that the second gate dopant is not implanted into the gate electrode material on the left side surface of the pillar. The first gate dopant is different from the second gate dopant such that a threshold voltage at the gate electrode material of the field effect transistor is less than about 0.4 Volts. The present invention may be used to particular advantage when the first gate dopant is an N-type dopant, and when the second gate dopant is a P-type dopant.

Abstract translation: 为了在SOI（绝缘体上半导体）技术的半导体衬底上制造场效应晶体管，在掩埋绝缘材料层上形成半导体材料柱。 该支柱具有顶面，左侧面，右侧面，前侧面和后侧面，该支柱具有宽度和长度。 在支柱的上表面上形成由硬掩模电介质材料构成的电介质结构。 第一栅极电介质形成在柱的左侧表面上，并且第二栅极电介质沿着柱的长度的栅极长度形成在柱的右侧表面上。 栅电极材料沉积在电介质结构上，并且在第一栅极电介质和第二栅极电介质上沉积在柱的顶表面和柱的左侧和右侧表面处的柱，用于柱的栅极长度。 在柱的左侧表面上以与栅电极材料相对的角度注入第一栅极掺杂剂，使得第一栅极掺杂剂不被注入到柱的右侧表面上的栅电极材料中。 此外，在柱的右侧表面上以与栅电极材料相对的角度注入第二栅极掺杂剂，使得第二栅极掺杂剂不被注入到柱的左侧表面上的栅电极材料中。 第一栅极掺杂剂不同于第二栅极掺杂剂，使得场效应晶体管的栅电极材料处的阈值电压小于约0.4伏特。 当第一栅极掺杂剂是N型掺杂剂时，并且当第二栅极掺杂剂是P型掺杂剂时，本发明可以被用于特别有利。

公开(公告)号：US06297115B1

公开(公告)日：2001-10-02

申请号：US09303696

申请日：1999-05-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/7834 ,  H01L21/2255 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28044 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual-amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region is between 10-15 nm below the top surface of the substrate, and the deep amorphous region is between 60-120 nm below the top surface of the substrate. The shallow amorphous region helps to reduce ion-implantation channeling effects, and the deep amorphous region helps to getter point defects generated during dopant implantation. The process can be utilized for P-channel or N-channel metal field effects semiconductor transistors (MOSFETS) and has a very low thermal budget.

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法利用双非晶化技术。 该技术产生了300nm厚的浅非晶区和深非晶区。 浅非晶区域在衬底的顶表面之下10-15nm之间，深非晶区域在衬底顶表面之下的60-120nm之间。 浅非晶区域有助于减少离子注入沟道效应，并且深非晶区域有助于在掺杂剂注入期间产生的吸气点缺陷。 该过程可用于P沟道或N沟道金属场效应半导体晶体管（MOSFET），并具有非常低的热预算。

公开(公告)号：US06265250B1

公开(公告)日：2001-07-24

申请号：US09406169

申请日：1999-09-23

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2184

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2026 ,  H01L21/76264 ,  H01L21/76283

Abstract: A method for making a ULSI MOSFET using silicon on insulator (SOI) principles includes masking regions of an amorphous silicon film on a substrate and exposing intended active regions. Laser energy is directed against the intended active regions to anneal these regions without annealing the masked regions, thereby increasing production throughput and decreasing defect density.

Abstract translation: 使用绝缘体上硅（SOI）原理制造ULSI MOSFET的方法包括在衬底上的非晶硅膜的掩蔽区域并暴露预期的有源区域。 激光能量针对预期的有源区域进行退火以退火这些区域而不对掩蔽区域进行退火，由此增加生产量并降低缺陷密度。