公开(公告)号：US20130075870A1

公开(公告)日：2013-03-28

申请号：US13622573

申请日：2012-09-19

Applicant: STMicoelectronics (Crolles 2) SAS ,  STMicroelectronics SA,

Inventor： Didier Dutartre ,  Michel Marty ,  Sebastien Jouan

IPC: H01L21/3105 ,  H01L23/58

CPC classification number: H01L21/76898 ,  H01L21/76251

Abstract: A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.

Abstract translation: 一种器件和相应的制造方法包括在下部区域和上部区域之间具有中间层的垂直堆叠。 中间层由保护层延伸。 垂直堆叠具有自由侧面，下部区域，上部区域和保护层暴露在该侧面上。

公开(公告)号：US20040266112A1

公开(公告)日：2004-12-30

申请号：US10852057

申请日：2004-05-24

Applicant: STMicroelectronics SA

Inventor： Thomas Skotnicki ,  Emmanuel Josse

IPC: H01L021/332 ,  H01L021/336 ,  H01L021/4763 ,  H01L021/8238

CPC classification number: H01L29/66666 ,  H01L29/165 ,  H01L29/7827

Abstract: The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1, PL2 extending between the source and drain regions, and forming two very fine pillars.

公开(公告)号：US20040257467A1

公开(公告)日：2004-12-23

申请号：US10782651

申请日：2004-02-19

Applicant: STMICROELECTRONICS SA

Inventor： Marina Nicolas

IPC: H04N011/20

CPC classification number: H04N7/012 ,  H04N5/144 ,  H04N7/0137

Abstract: The invention provides for a process and a device for de-interlacing a video signal, wherein at output (S) is produced a signal (Sde) of video images de-interlaced by interpolating the pixels missing from the interlaced video signal presented at input (E), the interpolation on the output signal (Sde) being composed selectively (10) from a spatial interpolation (6), based on a transition detection and from a temporal interpolation (8) with a decision being made on the variable degree of presence of spatial interpolation and/or of temporal interpolation in the output signal (Sde), the decision being made as a function of a motion detection in the relevant area of the image, wherein the decision is made additionally as a function of a detection of the detail (2) in a relevant area of the image.

Abstract translation: 本发明提供了一种用于对视频信号进行去隔行扫描的过程和设备，其中在输出（S）处产生视频图像的信号（Sde），该视频图像通过内插来自在输入处呈现的隔行视频信号丢失的像素而被去隔行扫描 E），基于转移检测和来自对可变存在度的决定的时间插值（8），从空间插值（6）选择性地（10）地输出输出信号（Sde）上的内插 在所述输出信号（Sde）中进行空间插值和/或时间内插的判定，所述判定作为所述图像的相关区域中的运动检测的函数，其中，所述判定作为附加检测的函数 细节（2）在图像的相关区域。

公开(公告)号：US20040246997A1

公开(公告)日：2004-12-09

申请号：US10824932

申请日：2004-04-15

Applicant: STMicroelectronics SA

Inventor： Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

IPC: H04L005/16

CPC classification number: G06F13/385 ,  H04L7/044 ,  H04L7/046

Abstract: A asynchronous frame receiver includes an input for receiving asynchronous frames. The asynchronous frames include standard characters, and a header that has a data bit length greater than a data bit length of the standard characters. A break character detection unit detects the break character. A standard character processing unit for detecting the standard characters is activated by the break character detection unit based upon the break character being detected.

Abstract translation: 异步帧接收器包括用于接收异步帧的输入。 异步帧包括标准字符和数据位长度大于标准字符的数据位长度的报头。 中断字符检测单元检测断点字符。 用于检测标准字符的标准字符处理单元由断点字符检测单元基于检测到的断点字符来激活。

公开(公告)号：US20040132260A1

公开(公告)日：2004-07-08

申请号：US10714440

申请日：2003-11-14

Applicant: STMicroelectronics SA

Inventor： Damien Lenoble

IPC: H01L021/336

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665

Abstract: A process for fabricating an integrated circuit includes forming a gate on a crystalline silicon substrate, and amorphizing a region of the substrate to obtain an amorphous silicon region. Dopant is implanted in a subregion lying substantially within the amorphous silicon region of the substrate to form drain and source extensions. A source and drain are then formed at a low temperature.

Abstract translation: 一种用于制造集成电路的工艺包括在晶体硅衬底上形成栅极，并使基片的区域非晶化以获得非晶硅区域。 掺杂剂被植入在基本上位于衬底的非晶硅区域内的子区域中以形成漏极和源极延伸。 然后在低温下形成源极和漏极。

公开(公告)号：US20040113665A1

公开(公告)日：2004-06-17

申请号：US10688208

申请日：2003-10-17

Applicant: STMicroelectronics SA

Inventor： Loic Joet ,  Sebastien Dedieu ,  Eric Andre ,  Daniel Saias

IPC: H03L007/06

CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/183 ,  H03L7/199 ,  H03L2207/18

Abstract: A method for generating a signal with a frequency equal to a product of a reference frequency and a real number includes providing an output signal from an oscillator, and performing a first integer division of a frequency of the output signal by a first integer divider to obtain a first intermediate signal. A first measurement signal representative of a time difference between the first intermediate signal and a reference signal having the reference frequency is determined. The method further includes generating a first comparison signal derived from the first measurement signal, and generating a second comparison signal dependent on a period of the reference signal, on integer and decimal parts of the real number and on the first integer divider. The first and second comparison signals are compared to obtain an error signal representative of a time difference between a period of a current output signal and the period of the reference signal. The first integer division is deactivated to deliver an error signal to the input of the oscillator, with the output signal from the oscillator forming the desired signal with a frequency equal to the product of the reference frequency and the real number.

Abstract translation: 用于产生频率等于参考频率和实数的乘积的信号的方法包括提供来自振荡器的输出信号，以及通过第一整数分频器对输出信号的频率进行第一整数除法以获得 第一中间信号。 确定代表第一中间信号和具有参考频率的参考信号之间的时间差的第一测量信号。 该方法还包括生成从第一测量信号导出的第一比较信号，以及根据参考信号的周期，在实数的整数和小数部分以及第一整数分频器上产生第二比较信号。 比较第一和第二比较信号以获得表示当前输出信号的周期与参考信号周期之间的时间差的误差信号。 第一个整数除法被去激活以向振荡器的输入端发送一个误差信号，来自振荡器的输出信号形成期望的信号，其频率等于参考频率和实数的乘积。

公开(公告)号：US20040062108A1

公开(公告)日：2004-04-01

申请号：US10383153

申请日：2003-03-06

Applicant: STMicroelectronics SA

Inventor： Cyrille Dray ,  Phillipe Gendrier ,  Richard Fournel

IPC: G11C007/00

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

Abstract: The semiconductor memory device includes a non-volatile programmable and electrically erasable memory cell with a single layer of gate material and a floating gate transistor and a control gate, within an active semiconducting area formed in a region of the substrate and delimited by an isolation region. The layer of gate material in which the floating gate is made extends integrally above the active area without overlapping part of the isolation region, and the transistor is electrically isolated from the control gate by PN junctions that will be inverse polarized.

Abstract translation: 半导体存储器件包括具有单层栅极材料的非易失性可编程和电可擦除存储单元，以及浮置栅极晶体管和控制栅极，该有源半导体区域形成在衬底的区域中并由隔离区限定 。 其中制造浮栅的栅极材料层在有源区域上整体地延伸而不重叠隔离区的一部分，并且晶体管通过将被反极化的PN结与控制栅极电隔离。

公开(公告)号：US20040057265A1

公开(公告)日：2004-03-25

申请号：US10616413

申请日：2003-07-09

Applicant: STMicroelectronics SA ,  Laboratoire Materiaux et Microelectronique de Provence (L2MP)

Inventor： Jean-Michel Mirabel ,  Rachid Bouchakour ,  Pierre Canet ,  Romain Laffont ,  Juliano Razafindramora

IPC: G11C027/00

CPC classification number: G11C16/14

Abstract: A memory cell in an EEPROM includes a floating gate transistor that includes a first conducting terminal and a control gate. A method of controlling the memory cell includes setting a state of the memory cell by simultaneously applying voltage pulses of opposite polarities respectively to the first conducting terminal and to the control gate. The voltage pulses including a first portion having a first slope and a second portion having a second slope, wherein the second slope is based upon the polarities of the voltage pulses. The method allows the amplitude of the voltage pulses to be reduced.

Abstract translation: EEPROM中的存储单元包括具有第一导电端子和控制栅极的浮栅晶体管。 控制存储单元的方法包括：通过同时向第一导电端子和控制栅极施加相反极性的电压脉冲来设定存储单元的状态。 电压脉冲包括具有第一斜率的第一部分和具有第二斜率的第二部分，其中第二斜率基于电压脉冲的极性。 该方法允许降低电压脉冲的幅度。

公开(公告)号：US20040052144A1

公开(公告)日：2004-03-18

申请号：US10325617

申请日：2002-12-20

Applicant: STMicroelectronics N.V. ,  STMicroelectronics SA

Inventor： Freidbert Berens ,  Michael J. Thul ,  Franck Gilbert ,  Norbert Wehn

IPC: G11C007/00

CPC classification number: H03M13/6566 ,  H03M13/2771

Abstract: In a particular embodiment using a distributed architecture, the electronic device comprises a source memory means partitioned in N elementary source memories for storing a sequence of input data, processing means clocked by a clock signal and having N outputs for producing per cycle of the clock signal N data respectively associated to N input data respectively stored in the N elementary source memories at relative source addresses, N single port target memories, N interleaving tables containing for each relative source address the number of one target memory and the corresponding relative target address therein, N cells connected in a ring structure, each cell being further connected between one output of the processing means, one interleaving table, and the port of one target memory, each cell being adapted to receive data from said output of the processing means and from its two neighbouring cells or to write at least some of these received data sequentially in the associated target memory, in accordance with the contents of said interleaving tables.

Abstract translation: 在使用分布式架构的特定实施例中，电子设备包括在N个基本源存储器中分区的源存储器装置，用于存储输入数据序列，由时钟信号计时的处理装置，并具有用于产生每个时钟信号周期的N个输出 N个数据分别与N个输入数据相关联地存储在相对源地址的N个基本源存储器中，N个单端口目标存储器，N个交织表，每个相对源地址包含一个目标存储器的数目和其中的对应的相对目标地址， N个单元以环形结构连接，每个单元进一步连接在处理装置的一个输出端，一个交织表和一个目标存储器的端口之间，每个单元适于从处理装置的输出端接收数据， 两个相邻小区或者在相关联的小区中顺序地写入这些接收的数据中的至少一些 t存储器，根据所述交织表的内容。

公开(公告)号：US20040012486A1

公开(公告)日：2004-01-22

申请号：US10453454

申请日：2003-06-03

Applicant: STMicroelectronics SA

Inventor： Christophe Mani

IPC: H04Q005/22

CPC classification number: G06K7/10029 ,  G06K7/0008

Abstract: An anti-collision method to identify and select contactless electronic modules (MDL) by a terminal is provided. A module may generate a random identification number prior to a communication, and respond to a general or complementary identification request on a time slot that varies according to its identification number. A non-selected module may generate a new random identification number when it receives a complementary identification request. Thus, the time slot of a non-selected module provided in response to a complementary identification request is not statistically the same as its time slot in response to a previous identification request, and it varies according to its identification number (ID).

Abstract translation: 提供了一种通过终端识别和选择非接触电子模块（MDL）的防碰撞方法。 模块可以在通信之前生成随机标识号，并且在根据其标识号变化的时隙上响应一般或补充的标识请求。 未选择的模块可以在接收到补充标识请求时产生新的随机标识号。 因此，响应于补充识别请求而提供的未选择模块的时隙在响应于先前的识别请求时与其时隙在统计上不相同，并且根据其标识号（ID）而变化。