公开(公告)号：US20220137220A1

公开(公告)日：2022-05-05

申请号：US17481960

申请日：2021-09-22

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Cedric Tubert

IPC: G01S17/89 ,  G01S7/4865

Abstract: In an embodiment a method for acquiring a depth map by indirect time of flight in a network of photosensitive pixels segmented into groups of pixels includes performing at least one capture during which the pixels of the network are controlled by a demodulation signal and introducing phase shifts into the demodulation signal at different values distributed in each group of pixels.

公开(公告)号：US20220102591A1

公开(公告)日：2022-03-31

申请号：US17485010

申请日：2021-09-24

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Olivier ZANELLATO ,  Remi BRECHIGNAC ,  Jerome LOPEZ

IPC: H01L33/48 ,  H01L31/0203 ,  H01L31/18 ,  H01L33/00

Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.

公开(公告)号：US11281807B2

公开(公告)日：2022-03-22

申请号：US16403275

申请日：2019-05-03

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Rosalino Critelli ,  Giuseppe Guarnaccia ,  Delphine Le-Goascoz ,  Nicolas Anquet

IPC: G06F21/72 ,  G06F3/06 ,  G06F11/10 ,  G06F13/16 ,  G06F21/57 ,  G06F21/85 ,  H04L9/08

Abstract: In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.

公开(公告)号：US11275589B2

公开(公告)日：2022-03-15

申请号：US16573299

申请日：2019-09-17

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Sebastien Metzger ,  Silvia Brini

IPC: G06F9/38 ,  G06F9/48 ,  G06F12/084 ,  G06F13/16

Abstract: A processor interacts with a memory set including a cache memory, a first memory storing at least a first piece of information in a first information group, and a second memory storing at least a second piece of information in a second information group. In response to a first cache miss and following a first request from the processor for the first piece of information, the first piece of information obtained from the first memory is supplied to the processor. After a second request from the processor for the second piece of information, the second piece of information obtained from the second memory is supplied to the processor, even if the first information group is currently being transferred from the first memory for loading into the cache memory.

公开(公告)号：US11271478B2

公开(公告)日：2022-03-08

申请号：US17099106

申请日：2020-11-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Xavier Branca

IPC: H02M3/07 ,  H02M1/08

Abstract: A charge pump generates an output voltage. A first circuit generates a pulse width-modulated signal as a function of a deviation between the output voltage and a setpoint voltage. A second circuit receives a periodic signal and conditions the supply of the periodic signal to a control input of the charge pump as a function of the state of the pulse width-modulated signal.

公开(公告)号：US20220069811A1

公开(公告)日：2022-03-03

申请号：US17412991

申请日：2021-08-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Denis COTTIN ,  Fabrice ROMAIN

IPC: H03K3/356 ,  H03K19/0185 ,  G09G3/3225

Abstract: An output potential level among two first levels is delivered according to an input level among two second levels. The output potential level is delivered at a first node connecting together first and second transistors electrically in series between two second nodes of application of the first levels. A first DC voltage defining a high limit for the control voltage of the first transistor is delivered by a first voltage generator powered by one of the second nodes. A second DC voltage defining a high limit for the control voltage of the second transistor is delivered by a second voltage generator controlled by a value representative of the first voltage and powered between the second nodes.

公开(公告)号：US20220018899A1

公开(公告)日：2022-01-20

申请号：US17375450

申请日：2021-07-14

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Etienne Auvray ,  Tommaso Melis ,  Philippe Sirito-Olivier

IPC: G01R31/311 ,  G01R31/28 ,  G01R15/22 ,  G01R19/00

Abstract: According to one aspect, an integrated circuit includes: an electronic module configured to generate a voltage at an output, and an electronic control circuit coupled to an output of the electronic module, the electronic control circuit comprising an emissive electronic component. The electronic control circuit is configured to cause the emissive electronic component to emit light radiation as a function of a value of the voltage at the output of the electronic module relative to a value of an operating voltage of the electronic module, and the operating voltage is specific thereto during normal operation of this electronic module. The light radiation emitted by the emissive electronic component is configured to diffuse to an outer face of the integrated circuit.

公开(公告)号：US20210391227A1

公开(公告)日：2021-12-16

申请号：US17345600

申请日：2021-06-11

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Richard REMBERT ,  Didier SIGNORET ,  Olivier FRANIATTE

IPC: H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic device includes a support substrate. A face is covered with a soldermask layer. At least part of the soldermask layer includes roughnesses providing a rough grip surface. An electronic die is mounted on the support substrate. A molding resin encapsulates the electronic die and partially or completely covers the soldermask layer.

公开(公告)号：US20210382964A1

公开(公告)日：2021-12-09

申请号：US17410143

申请日：2021-08-24

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED

Inventor： John Kevin Moore ,  Sam Lee ,  Pascal Mellot ,  Donald Baxter ,  Stuart McLeod ,  Kenneth Dargan

IPC: G06F17/18 ,  G01S7/4863 ,  G06F11/07 ,  G01S17/10 ,  G01S7/4865 ,  G01S7/487 ,  G01S7/497

Abstract: A method includes receiving a histogram output from a detector sensor, and calculating a median point of a pulse waveform within the histogram. The pulse waveform has an even probability distribution over at least one quantization step of the histogram around the median point. A corresponding apparatus can include a detector sensor and a co-processor coupled to the detector sensor.

公开(公告)号：US11196419B2

公开(公告)日：2021-12-07

申请号：US16870276

申请日：2020-05-08

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Vincent Pinon

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K3/356 ,  H03K19/003

Abstract: A voltage level shifter device an input stage and an output stage. The input stage is configured to lower one of the first and second output terminals to the low level according to the level of the input voltage. A latch circuit includes a first branch having a first PMOS transistor and a second PMOS transistor coupled in series coupled between a shifted-high-level voltage supply terminal and the first output terminal and a second branch having a third PMOS transistor an a fourth PMOS transistor coupled in series between the shifted-high-level voltage supply terminal and the second output terminal. The first output terminal is a gate of the second PMOS transistor and to a gate of the third PMOS transistor. The second output terminal is coupled a gate of the fourth PMOS transistor and to a gate of the first PMOS transistor.