公开(公告)号：US20220102591A1

公开(公告)日：2022-03-31

申请号：US17485010

申请日：2021-09-24

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Olivier ZANELLATO ,  Remi BRECHIGNAC ,  Jerome LOPEZ

IPC: H01L33/48 ,  H01L31/0203 ,  H01L31/18 ,  H01L33/00

Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.

公开(公告)号：US20190148334A1

公开(公告)日：2019-05-16

申请号：US16249122

申请日：2019-01-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE ,  Asma HAJJI ,  Fabien QUERCIA ,  Jerome LOPEZ

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/552

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

公开(公告)号：US20240072214A1

公开(公告)日：2024-02-29

申请号：US18503025

申请日：2023-11-06

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Olivier ZANELLATO ,  Remi BRECHIGNAC ,  Jerome LOPEZ

IPC: H01L33/48 ,  H01L31/0203 ,  H01L31/18 ,  H01L33/00

CPC classification number: H01L33/483 ,  H01L31/0203 ,  H01L31/18 ,  H01L33/005

Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.

公开(公告)号：US20250070081A1

公开(公告)日：2025-02-27

申请号：US18947819

申请日：2024-11-14

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE ,  Asma HAJJI ,  Fabien QUERCIA ,  Jerome LOPEZ

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/552

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

公开(公告)号：US20240258184A1

公开(公告)日：2024-08-01

申请号：US18630676

申请日：2024-04-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jerome LOPEZ

IPC: H01L23/31 ,  H01L23/10 ,  H01L23/12 ,  H01L33/52

CPC classification number: H01L23/3114 ,  H01L23/10 ,  H01L23/12 ,  H01L33/52

Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.

公开(公告)号：US20200227382A1

公开(公告)日：2020-07-16

申请号：US16835793

申请日：2020-03-31

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE ,  Asma HAJJI ,  Fabien QUERCIA ,  Jerome LOPEZ

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/31

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

公开(公告)号：US20230411271A1

公开(公告)日：2023-12-21

申请号：US18207954

申请日：2023-06-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Luc PETIT ,  Jerome LOPEZ ,  Karine SAXOD

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L23/3675 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/32245 ,  H01L24/32 ,  H01L2224/1413 ,  H01L2224/16225 ,  H01L24/73 ,  H01L2224/73253

Abstract: An electronic device includes an electronic chip located between a cover and an interconnection substrate. The electronic chip has contact pads located in front of a first surface of the interconnection substrate. At least one metal region (for example extending on the front surface) thermally couples at least one contact pad of the electronic chip to the cover.

公开(公告)号：US20230121780A1

公开(公告)日：2023-04-20

申请号：US18081884

申请日：2022-12-15

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE ,  Asma HAJJI ,  Fabien QUERCIA ,  Jerome LOPEZ

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/31

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

公开(公告)号：US20190088562A1

公开(公告)日：2019-03-21

申请号：US16133065

申请日：2018-09-17

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Malta) Ltd

Inventor： Jerome LOPEZ ,  Roseanne DUCA

IPC: H01L23/10 ,  H01L23/498 ,  H01L21/50 ,  H01L23/31

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L23/3121 ,  H01L23/49838

Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.

公开(公告)号：US20240087977A1

公开(公告)日：2024-03-14

申请号：US18244534

申请日：2023-09-11

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Jerome LOPEZ

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498

CPC classification number: H01L23/3672 ,  H01L23/3735 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16055 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/18161 ,  H01L2924/351

Abstract: An integrated circuit includes an electronic chip having a face covered with a thermal interface material layer. A heat sink includes a mounting area fixed to the chip via the thermal interface material layer. The heat sink includes open notches extending into the mounting area to delimit fins separated from each other by the open notches.