公开(公告)号：US20190146029A1

公开(公告)日：2019-05-16

申请号：US16184859

申请日：2018-11-08

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Yann BACHER ,  Nicolas FROIDEVAUX

IPC: G01R31/28 ,  H04B17/10

Abstract: A method of testing a first circuit, including: a) applying a first signal between two terminals of the first circuit, the first circuit being powered off; and b) verifying that radio frequency waves transmitted by the first circuit correspond to an expected transmission.

公开(公告)号：US20190140176A1

公开(公告)日：2019-05-09

申请号：US16184246

申请日：2018-11-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck ARNAUD ,  David GALPIN ,  Stephane ZOLL ,  Olivier HINSINGER ,  Laurent FAVENNEC ,  Jean-Pierre ODDOU ,  Lucile BROUSSOUS ,  Philippe BOIVIN ,  Olivier WEBER ,  Philippe BRUN ,  Pierre MORIN

IPC: H01L45/00 ,  H01L27/24

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

公开(公告)号：US20190137302A1

公开(公告)日：2019-05-09

申请号：US16237938

申请日：2019-01-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Vincent ONDE

IPC: G01D5/249 ,  G01D5/347 ,  G01D4/00

Abstract: A rotary element is equipped with a pattern representing a reflected binary code on at least three bits. A detection circuit is configured to sense the pattern and deliver an incident signal encoded in reflected binary code on at least three bits. The incident signal is converted by a transcoding circuit into an intermediate signal encoded in reflected binary code on two bits. A decoding stage decodes the intermediate signal and outputs at least one clock signal representing the amount of rotation of the rotary element and a direction signal representing the direction of rotation. A processing circuit determines the movement of the rotary element, and has at least one general purpose timer designed to receive the at least one clock signal and direction signal.

公开(公告)号：US10283563B2

公开(公告)日：2019-05-07

申请号：US15694463

申请日：2017-09-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

公开(公告)号：US20190122845A1

公开(公告)日：2019-04-25

申请号：US16222017

申请日：2018-12-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio Di-Giacomo ,  Brice Arrazat

IPC: H01H61/02 ,  B81B3/00 ,  H01H1/58 ,  H01H9/02

CPC classification number: H01H61/02 ,  B81B3/0021 ,  B81B2201/031 ,  B81B2203/053 ,  H01H1/58 ,  H01H9/02

Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.

公开(公告)号：US20190114400A1

公开(公告)日：2019-04-18

申请号：US16150810

申请日：2018-10-03

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Stefano Lunghi ,  Albert Martinez

IPC: G06F21/12 ,  G06F21/14 ,  G06F12/14 ,  G06F21/60 ,  G06F21/72 ,  G06F21/74 ,  H04L9/06 ,  G06F9/445

Abstract: An electronic device includes: a non-volatile memory configured to store data including encrypted data; and a digital circuit. The digital circuit includes: a microprocessor configured to access the non-volatile memory and an internal memory; and a decryption circuit arranged on an interconnect network identifying an internal data path for exchanging the data between the non-volatile memory and the microprocessor, and connected to a memory controller of the non-volatile memory for receiving blocks of data from the non-volatile memory, the decryption circuit being configured to: perform a decryption on the fly of blocks of the data read from the non-volatile memory to obtain read decrypted data; generate first decryption masks corresponding to first blocks of data being read from the non-volatile memory at a given read address; and generate second decryption masks corresponding to second blocks of data to be read from the non-volatile memory at a next estimated read address.

公开(公告)号：US20190113897A1

公开(公告)日：2019-04-18

申请号：US16155355

申请日：2018-10-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA

IPC: G05B19/042 ,  H02J7/00

Abstract: A system, supplied by a power supply, is switched into standby mode by an electronic device that includes a charging input coupled to a charge voltage obtained from the voltage delivered by the power supply. A first input is coupled to the power supply and a power supply output is coupled to the system. A storage capacitive element is coupled to the charging input and configured to be charged by the charge voltage. A switching circuit, coupled between the first input and the power supply output, disconnects the power supply output from the first input when the voltage across the terminals of the storage capacitive element is higher than a threshold. A discharge circuit discharges the storage capacitive element so that the capacitor voltage becomes lower than the threshold. The switching circuit further re-connects the first input to the power supply output at the end of the discharge period.

公开(公告)号：US10263768B2

公开(公告)日：2019-04-16

申请号：US15354016

申请日：2016-11-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yannick Teglia

IPC: H04L9/06 ,  H04L9/00 ,  H04L9/08 ,  H04L9/30

Abstract: A method for protecting a ciphering algorithm executing looped operations on bits of a first quantity and on a first variable initialized by a second quantity, wherein, for each bit of the first quantity, a random number is added to the state of this bit to update a second variable maintained between two thresholds.

公开(公告)号：US20190044758A1

公开(公告)日：2019-02-07

申请号：US16157428

申请日：2018-10-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Arnal ,  Roland Van Der Tuijn

IPC: H04L25/02 ,  H04B10/079 ,  G06F13/40

CPC classification number: H04L25/0262 ,  G06F13/4081 ,  H04B10/0795

Abstract: A method can be used for transmission of at least one packet of at least one bit over a serial link capable of taking two different states respectively associated with the two possible logical values of the at least one transmitted bit. Starting from a transmission start time of the at least one bit and up to the expiration of a first portion of a bit time associated with the at least one bit, the link is placed in one of its states depending on the logical value of the at least one bit. Upon the expiration of the first portion of this bit time, a first additional transition is generated over the link so as to place the link in its other state up to the expiration of the bit time.

公开(公告)号：US20190027447A1

公开(公告)日：2019-01-24

申请号：US16036639

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/00 ,  H01L23/528 ,  H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/45 ,  H01L29/08

CPC classification number: H01L23/573 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/4916

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.