公开(公告)号：US20040054514A1

公开(公告)日：2004-03-18

申请号：US10447776

申请日：2003-05-29

Applicant: STMicroelectronics SA

Inventor： Philippe Flatresse ,  Mario Casu

IPC: G06F017/50 ,  H03K019/20

CPC classification number: G06F17/5022 ,  G06F17/5036

Abstract: A method for characterizing a CMOS logic cell of the partially depleted silicon-on-insulator type (PD-SOI) may include modeling the logic cell and determining internal potentials of transistors of the cell in a dynamic equilibrium state based upon a functional simulation of the modeled cell. This may be done using a binary stimulation signal having an initial logic value. The dynamic equilibrium state may be based upon a cancellation, to within a precision error, of the sum of the squares of variations in the quantities of charge in floating substrates of the transistors taken over a period of two successive transitions of the stimulation signal.

Abstract translation: 用于表征部分耗尽的绝缘体上硅类型（PD-SOI）的CMOS逻辑单元的方法可以包括对动态平衡状态下的逻辑单元建模并确定单元的晶体管的内部电位，该功能模拟基于 建模细胞。 这可以使用具有初始逻辑值的二进制刺激信号来完成。 动态平衡状态可以基于在刺激信号的两个连续转换周期内所采用的晶体管的浮动基板中的电荷量的变化平方和的精度误差内的抵消。

公开(公告)号：US20040047414A1

公开(公告)日：2004-03-11

申请号：US10465532

申请日：2003-06-19

Applicant: STMicroelectronics SA ,  STMicroelectronics N.V.

Inventor： Didier Helal ,  Fritz Lebowsky

IPC: H03K007/04 ,  H03K007/06

CPC classification number: H04B1/7174 ,  H03K7/04 ,  H04L25/4902

Abstract: A controllable pulse generator generates the pulses of the signal which are respectively contained in successive time windows, and a control device formulates a control signal for the generator including, for each pulse, an indication of its position in the corresponding window. The control device includes a processor to deliver for each time window, at a delivery frequency Fe greater than the pulse repetition frequency, successive groups of N bits together defining a digital cue of position of a pulse inside the window. Also, a converter converts this digital position cue into the control signal temporally spread over the length (T) of the window and including the indication of position at an instant corresponding to the digital position cue. This makes it possible to position the pulse inside its window with a temporal precision equal to 1/N.Fe.

Abstract translation: 可控脉冲发生器产生分别包含在连续时间窗口中的信号脉冲，并且控制装置为发生器制定一个控制信号，包括对于每个脉冲，其对应的窗口中其位置的指示。 控制装置包括处理器，用于以大于脉冲重复频率的传送频率Fe传送每个时间窗口，连续的N位组一起定义窗口内的脉冲位置的数字提示。 此外，转换器将该数字位置提示转换成在窗口的长度（T）上暂时分布的控制信号，并且包括在对应于数字位置提示的时刻的位置指示。 这使得可以将脉冲定位在其窗口内，时间精度等于1 / N.Fe。

公开(公告)号：US20040017722A1

公开(公告)日：2004-01-29

申请号：US10438733

申请日：2003-05-15

Applicant: STMicroelectronics SA

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink ,  Jean Devin

IPC: G11C007/00

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/3418

Abstract: The present invention relates to a page-erasable FLASH memory including a memory array having a plurality of pages each with floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, and the application of a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector forming a page to be erased. According to the present invention, the word line decoder includes a unit for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased.

公开(公告)号：US20020171494A1

公开(公告)日：2002-11-21

申请号：US10102402

申请日：2002-03-19

Applicant: STMicroelectronics, SA

Inventor： Pascal Debaty

IPC: H03F001/14

CPC classification number: H03F1/083

Abstract: A circuit for splitting poles between a first stage and a second inverting voltage-amplifier stage of an electronic circuit, comprises, in series between the output of the first stage and the output of the second stage, and in that order, a first capacitor, a second capacitor and a resistor. The circuit further comprises a voltage-divider bridge which is connected between a terminal delivering a substantially constant voltage and the output of the first stage. The output of the voltage-divider bridge is linked to the common node between the first capacitor and the second capacitor, in such a way that a first resistor of the voltage-divider bridge is connected in parallel with the first capacitor.

Abstract translation: 用于在电子电路的第一级和第二反相电压放大器级之间分离极的电路包括串联在第一级的输出和第二级的输出之间，并且依次包括第一电容器， 第二电容器和电阻器。 该电路还包括分压器桥，该分压器桥连接在提供基本上恒定的电压的端子和第一级的输出之间。 分压器桥的输出端连接到第一电容器和第二电容器之间的公共节点，使得分压器桥的第一电阻器与第一电容器并联连接。

公开(公告)号：US20010025344A1

公开(公告)日：2001-09-27

申请号：US09738548

申请日：2000-12-15

Applicant: STMicroelectronics SA.

Inventor： Yannick Teglia

IPC: G06F011/30

CPC classification number: G06F21/6218 ,  G06F21/755 ,  G06F2207/7219 ,  G06F2221/2123

Abstract: A method is provided for secured transfer of data from a first memory containing the data element to a second memory through a data bus that is connected between the first memory and the second memory. According to the method, a secret N-byte data element is transferred byte-by-byte through the data bus, with each byte transiting at least once on the data bus. Before each transfer of a byte of the secret data element, a current index ranging from 0 to Nnull1 is randomly chosen, with the current index corresponding to a place value of the byte to be transferred. At each transfer of a byte of the secret data element with a place value equal to the current index, a corresponding bit of an N-byte loading indicator is modified as a function of a loading mode, with the loading mode being an integer ranging from 0 to a first constant. The transfer of the secret data element is ended when the loading indicator takes a predetermined value.

Abstract translation: 提供了一种通过连接在第一存储器和第二存储器之间的数据总线将数据从包含数据元素的第一存储器安全地传送到第二存储器的方法。 根据该方法，秘密的N字节数据元素通过数据总线逐字节传送，每个字节在数据总线上至少一次传输一次。 在秘密数据元素的一个字节的每次传送之前，随机选择范围从0到N-1的当前索引，其中当前索引对应于要传送的字节的位置值。 在每个传输具有等于当前索引的位置值的秘密数据元素的一个字节的字节时，N字节加载指示符的相应位被修改为加载模式的函数，其中加载模式是从 0到第一个常数。 当加载指示符取预定值时，秘密数据元素的传送结束。

公开(公告)号：US20240015945A1

公开(公告)日：2024-01-11

申请号：US18347435

申请日：2023-07-05

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Olivier Weber ,  Kedar Janardan Dhori ,  Promod Kumar ,  Shafquat Jahan Ahmed ,  Christophe Lecocq ,  Pascal Urard

IPC: H10B10/00 ,  G11C11/417

CPC classification number: H10B10/12 ,  H10B10/18 ,  G11C11/417

Abstract: In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.

公开(公告)号：US11867570B2

公开(公告)日：2024-01-09

申请号：US17192438

申请日：2021-03-04

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Renan Lethiecq

IPC: G01K7/01 ,  G01K7/22 ,  G01K7/25 ,  H01L27/12 ,  H01C7/04 ,  G05F3/24 ,  H01C7/00 ,  H01L29/10 ,  H01L29/78

CPC classification number: G01K7/01 ,  G01K7/015 ,  G01K7/22 ,  G01K7/226 ,  G01K7/25 ,  G05F3/245 ,  H01C7/008 ,  H01C7/04 ,  H01L27/1203 ,  H01L29/1095 ,  H01L29/7831

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal imposes the drain-source current of the first transistor.

公开(公告)号：US20230393250A1

公开(公告)日：2023-12-07

申请号：US18320849

申请日：2023-05-19

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Jeremie TEYSSIER ,  Antoine DROUOT ,  Thibault AUGEY ,  Valerie PENA-LAROCHE

IPC: G01S7/4912 ,  G01S7/481 ,  G01S17/894 ,  G01S7/4915

CPC classification number: G01S7/4918 ,  G01S7/4816 ,  G01S17/894 ,  G01S7/4915

Abstract: An indirect time-of-flight measurement sensor includes a photosensitive pixel array configured to acquire a succession of images of a scene during a given exposure time. The sensor includes a control unit configured to control the acquisition of the succession of images by the pixel array and to define an exposure time for this acquisition based on a pixel saturation rate of the array, distances between the sensor and elements of the scene, and a standard deviation of the distances between the sensor and the elements of the scene.

公开(公告)号：US11837647B2

公开(公告)日：2023-12-05

申请号：US17685780

申请日：2022-03-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis Gauthier ,  Pascal Chevalier

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/732 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/732 ,  H01L21/26513

Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.

公开(公告)号：US20230318658A1

公开(公告)日：2023-10-05

申请号：US18174236

申请日：2023-02-24

Applicant: STMICROELECTRONICS SA ,  STIMICROELECTRONICS (GRENOBLE) SAS

Inventor： Gregoire Montjaux ,  Marc Houdebine

IPC: H04B5/00 ,  H04L7/033 ,  H03L7/099

CPC classification number: H04B5/0031 ,  H03L7/0992 ,  H03L7/0994 ,  H04L7/033

Abstract: A device is configured to receive a first carrier signal, and deliver a second carrier signal, and has a phase-locked loop including a first domain including an oscillator configured to generate a signal at a given frequency, and a circuit configured to generate information representative of the frequency of the signal generated by the oscillator, and to generate the second carrier signal and a clock signal, the first domain being clocked by the first carrier signal, a second domain, clocked by the clock signal, including a circuit configured to compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and to control the oscillator, a matching circuit configured to transfer information representative of the frequency of the signal generated by the oscillator from the first domain to the second domain.