Allergy inhibitor compositions and kits and methods of using the same
    522.
    发明申请
    Allergy inhibitor compositions and kits and methods of using the same 有权
    过敏抑制剂组合物及其使用方法

    公开(公告)号:US20070166335A1

    公开(公告)日:2007-07-19

    申请号:US11644435

    申请日:2006-12-22

    Abstract: Compositions and kits for inhibiting an allergic response against an allergenic protein are disclosed. The compositions comprise a eukaryotic cell expression vector containing nucleotide sequences encoding an allergenic protein or a polypeptide that comprises an antigenic epitope of said allergenic protein; and an allergenic protein or a polypeptide that comprises an antigenic epitope of the allergenic protein. The kits comprise a first container which comprises a eukaryotic cell expression vector containing nucleotide sequences encoding an allergenic protein or a polypeptide that comprises an antigenic epitope of the allergenic protein and a second container which comprises an allergenic protein or a polypeptide that comprises an antigenic epitope of said allergenic protein. Compositions and kits for inhibiting an allergic response against an flea allergenic protein; a feline allergenic protein; a canine allergenic protein; a dust mite allergenic protein; a peanut allergenic protein; a Japanese cedar allergenic protein; and a blomia tropicalis allergenic protein are disclosed. Methods if using such compositions and kits are also disclosed.

    Abstract translation: 公开了抑制对变应原性蛋白质的过敏反应的组合物和试剂盒。 所述组合物包含含有编码过敏原蛋白或包含所述变应原蛋白的抗原表位的多肽的核苷酸序列的真核细胞表达载体; 以及包含过敏原蛋白的抗原表位的变应原蛋白或多肽。 所述试剂盒包括第一容器,其包含含有编码过敏原蛋白的核苷酸序列的真核细胞表达载体或包含过敏原蛋白的抗原表位的多肽,以及第二容器,其包含过敏原蛋白或包含抗原表位的多肽 说过敏性蛋白质。 用于抑制针对跳蚤过敏原蛋白质的过敏反应的组合物和试剂盒; 猫过敏原蛋白; 犬过敏蛋白; 尘螨过敏原蛋白; 花生过敏蛋白; 日本雪松过敏蛋白; 并且公开了热带炎热带炎性过敏蛋白。 还公开了使用这些组合物和试剂盒的方法。

    SYSTEM AND METHOD FOR CALIBRATING A FEEDER FOR A SURFACE MOUNTING DEVICE
    524.
    发明申请
    SYSTEM AND METHOD FOR CALIBRATING A FEEDER FOR A SURFACE MOUNTING DEVICE 失效
    用于校准表面安装装置的进料器的系统和方法

    公开(公告)号:US20070097368A1

    公开(公告)日:2007-05-03

    申请号:US11309576

    申请日:2006-08-25

    CPC classification number: G01G13/24 G01G23/01 Y10T29/4913

    Abstract: A method for calibrating a feeder for a surface mounting device (SMD) includes the steps of: reading a standard coordinate value; setting controlling parameters including a predefined amount of materials to be delivered and a predefined range of a coordinate deviation; booting the feeder (22) to deliver materials via an operation controller (20); capturing delivered material images of the materials and gear images of the feeder via an image controller (24); calculating coordinate deviations of the captured images; analyzing whether a total delivered amount of the materials is equal to the predefined amount; and calibrating the feeder according to the calculated coordinate deviations if the total delivered amount of the materials is equal to the predefined amount. A system for calibrating a feeder for a surface mounting device (SMD) is also disclosed.

    Abstract translation: 用于校准表面安装装置(SMD)的馈送器的方法包括以下步骤:读取标准坐标值; 设置控制参数,包括预定量的要传递的材料和坐标偏差的预定范围; 引导馈送器(22)以经由操作控制器(20)传送材料; 经由图像控制器(24)捕获馈送器的材料和齿轮图像的传送材料图像; 计算拍摄图像的坐标偏差; 分析材料的总交付量是否等于预定量; 并且如果材料的总交付量等于预定量,则根据所计算的坐标偏差来校准进料器。 还公开了一种用于校准用于表面安装装置(SMD)的馈送器的系统。

    Graded junction high voltage semiconductor device
    525.
    发明申请
    Graded junction high voltage semiconductor device 有权
    分级结高压半导体器件

    公开(公告)号:US20070093028A1

    公开(公告)日:2007-04-26

    申请号:US11490407

    申请日:2006-07-19

    Applicant: Bin Wang

    Inventor: Bin Wang

    Abstract: A graded junction space decreasing an implant concentration gradient between n-well and p-well regions of a semiconductor device is provided for enhancing breakdown voltage in high voltage applications. Split or unified FOX regions may be provided overlapping with the graded junction space. By using a p-well blocking layer to separate the p-well(s) and the n-well, breakdown voltage characteristic is improved without the cost of an additional mask or process change.

    Abstract translation: 提供降低半导体器件的n阱和p阱区域之间的注入浓度梯度的分级结空间,用于增强高电压应用中的击穿电压。 分割或统一的FOX区域可以被提供为与分级结合空间重叠。 通过使用p阱阻挡层来分离p阱和n阱,可以提高击穿电压特性,而不需要额外的掩模或工艺变化的成本。

    Graded-junction high-voltage MOSFET in standard logic CMOS
    526.
    发明授权
    Graded-junction high-voltage MOSFET in standard logic CMOS 有权
    分级结高压MOSFET在标准逻辑CMOS

    公开(公告)号:US07145203B2

    公开(公告)日:2006-12-05

    申请号:US10884326

    申请日:2004-07-02

    Applicant: Bin Wang

    Inventor: Bin Wang

    CPC classification number: H01L29/7835 H01L29/0653 H01L29/1045 H01L29/42368

    Abstract: A high-voltage graded junction LDMOSFET includes a substrate of a first conductivity type, a well of the first conductivity type disposed in the substrate, a first region of a second conductivity type disposed in the well of the first conductivity type, a source terminal coupled to the first region of the second conductivity type, a well of the second conductivity type disposed in the substrate, a second region of the second conductivity type disposed in the well of the second conductivity type, a drain terminal coupled to the second region of the second conductivity type, a region of the first conductivity type disposed in the substrate, a body terminal coupled to the region of the first conductivity type, a graded-junction region formed of material of the first conductivity type separating the well of the first conductivity type and the well of the second conductivity type, the material of the first conductivity type in the graded-junction region doped at least an order of magnitude less than the wells, a dielectric layer disposed over the well of the first conductivity type, the graded-junction region and a portion of the well of the second conductivity type, a first isolator disposed in the well of the second conductivity type, the isolator including a dielectric material that is in contact with the dielectric layer, a second isolator disposed at least partially in the well of the second conductivity type, the second isolator including a dielectric material and isolating the second region of the second conductivity type from the region of the first conductivity type, and a gate disposed over the dielectric layer and a portion of the first isolator.

    Abstract translation: 高压梯度结LDMOSFET包括第一导电类型的衬底,设置在衬底中的第一导电类型的阱,设置在第一导电类型的阱中的第二导电类型的第一区域,源极端子耦合 到第二导电类型的第一区域,设置在基板中的第二导电类型的阱,设置在第二导电类型的阱中的第二导电类型的第二区域,耦合到第二导电类型的第二区域的漏极端子 第二导电类型,设置在基板中的第一导电类型的区域,耦合到第一导电类型的区域的主体端子,由第一导电类型的材料形成的分级接合区域,该第一导电类型的材料将第一导电类型的阱 和第二导电类型的阱,掺杂了至少一个数量级的渐变结区域中的第一导电类型的材料 小于所述阱的介质层,设置在所述第一导电类型的阱中的介电层,所述渐变接合区域和所述第二导电类型的阱的一部分,设置在所述第二导电类型的阱中的第一隔离器,所述隔离器 包括与电介质层接触的电介质材料,至少部分地设置在第二导电类型的阱中的第二隔离器,第二隔离器包括电介质材料,并将第二导电类型的第二区域与 第一导电类型和设置在电介质层上的栅极和第一隔离器的一部分。

    Program installation system and method using the same
    527.
    发明申请
    Program installation system and method using the same 审中-公开
    程序安装系统及使用方法

    公开(公告)号:US20060155838A1

    公开(公告)日:2006-07-13

    申请号:US11092727

    申请日:2005-03-30

    CPC classification number: G06F9/4416

    Abstract: A program installation system and method allowing a diskless computer device to perform program installation is proposed, the method comprising: establishing a booting unit and a memory section in the computer device, a DHCP server comprising a network information database for storing network setting information, and a storage server comprising a program storage section for storing at least one program and a information storage section for storing information sent from the network system; issuing a booting request by the booting unit; the DHCP server sending network setting information to the computer device in response to receiving the booting request; the computer device storing the network setting information in the memory section and issuing a program installation request based on the stored network setting information; the storage server storing information of the memory section in the information storage section and storing a network address of the storage server to the booting unit in response to receiving the program installation request; and the computer device being rebooted and connected to the storage server according to the stored network address, allowing the computer device to perform the program installation process by accessing the program storage section of the storage server.

    Abstract translation: 提出了一种允许无盘计算机设备执行程序安装的程序安装系统和方法,所述方法包括:在计算机设备中建立引导单元和存储器部分,包括用于存储网络设置信息的网络信息数据库的DHCP服务器,以及 存储服务器,包括用于存储至少一个程序的程序存储部分和用于存储从所述网络系统发送的信息的信息存储部分; 由引导单元发出引导请求; DHCP服务器响应于接收到引导请求向计算机设备发送网络设置信息; 所述计算机设备将所述网络设置信息存储在所述存储器部分中,并基于所存储的网络设置信息发布程序安装请求; 所述存储服务器将所述存储器部分的信息存储在所述信息存储部分中,并且响应于接收到所述程序安装请求而将所述存储服务器的网络地址存储到所述引导单元; 并且计算机设备根据存储的网络地址重新启动并连接到存储服务器,从而允许计算机设备通过访问存储服务器的程序存储部分来执行程序安装过程。

    Digitized image stabilization using energy analysis method
    529.
    发明申请
    Digitized image stabilization using energy analysis method 有权
    使用能量分析方法进行数字化图像稳定

    公开(公告)号:US20060146139A1

    公开(公告)日:2006-07-06

    申请号:US11028744

    申请日:2005-01-04

    CPC classification number: H04N5/23248

    Abstract: A method and an apparatus are provided for image stabilization for the output of analog-to-digital converters (ADC) and for phase-locked loops (PLL). The digital coding at the output of ADCs and PLLs is filtered by this method and apparatus to eliminate the noise which has contaminated the coding. The noise sources are noise picked up by the cable, system board noise, ADC power and ground noise paths, and switching noise. The differences of energy level of sequential pixels in the ADC and PLL digital outputs used in image displays are used to decide if correction is required. The method of image noise filtering is compatible with programmable circuitry. This allows the method to be tuned for optimal image stabilization.

    Abstract translation: 提供了一种用于模数转换器(ADC)和锁相环(PLL)的输出的图像稳定的方法和装置。 通过该方法和装置对ADC和PLL输出端的数字编码进行滤波,以消除已经污染编码的噪声。 噪声源是由电缆拾取的噪声,系统板噪声,ADC功率和接地噪声路径以及开关噪声。 在图像显示中使用的ADC和PLL数字输出中的顺序像素的能级差异用于确定是否需要校正。 图像噪声滤波的方法与可编程电路兼容。 这样可以调整该方法以获得最佳图像稳定性。

    High voltage FET gate structure
    530.
    发明申请
    High voltage FET gate structure 有权
    高压FET栅极结构

    公开(公告)号:US20060001050A1

    公开(公告)日:2006-01-05

    申请号:US11138888

    申请日:2005-05-26

    Abstract: A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.

    Abstract translation: 用于在高电压下操作的FET器件包括分别掺杂有第一类型和第二类型的植入物的衬底,衬底内的第一阱和第二阱。 第一和第二阱限定p-n结。 第二阱内的场氧化物层限定了接收漏极接触的第一表面区域。 第三阱至少部分地位于第一阱中,包括第二类型的掺杂植入物,并且适于接收源极接触。 这样,第三井在第一井内定义了自身与第二井之间的通道。 通道上设置一个门。 栅极的至少第一部分设置在p-n结上方,并且包括第一类型的掺杂植入物。 许多排列允许掺杂栅极的其余部分。

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