公开(公告)号：US20210109711A1

公开(公告)日：2021-04-15

申请号：US17038774

申请日：2020-09-30

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Rene Peyrard ,  Fabrice Romain ,  Jean-Michel Derien ,  Christophe Eichwald

IPC: G06F7/57 ,  G06F7/76 ,  G06F9/30 ,  H03K19/21

Abstract: An embodiment relates to a method for processing masked data using a processor comprising an arithmetic and logic unit, in which the masked data remain masked during their processing in the arithmetic and logic unit.

公开(公告)号：US10979063B2

公开(公告)日：2021-04-13

申请号：US16862297

申请日：2020-04-29

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Sandrine Nicolas ,  Damien Giot ,  Serge Ramet ,  Reiner Welk

IPC: H03M1/38 ,  H03M1/12 ,  H03M1/44

Abstract: An electronic circuit comprises capacitive structures that are connected to one or a plurality of nodes, where each of the capacitive structures is formed by a capacitor or by a plurality of capacitors electrically connected in parallel. The electronic circuit further comprises additional capacitors that are each connected to the one or plurality of nodes. For at least one distance between capacitors, the capacitive structures have a same average of values defined, for each capacitor of each capacitive structure, by the number of capacitors of the circuit connected to the one or plurality of nodes and located at the distance from the capacitor of the capacitive structure.

公开(公告)号：US10978400B2

公开(公告)日：2021-04-13

申请号：US16390889

申请日：2019-04-22

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Eric Saugier

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/498

Abstract: The disclosure concerns a semiconductor chip, which may be an interposer, having conductive through vias having a parallelepipedal shape.

公开(公告)号：US10970229B2

公开(公告)日：2021-04-06

申请号：US16296706

申请日：2019-03-08

Applicant: STMicroelectronics (Grenoble 2) SAS ,  Technological Educational Institute of Crete

Inventor： Antonio-Marcello Coppola ,  Georgios Kornaros ,  Miltos Grammatikakis

IPC: G06F12/10 ,  G06F9/54 ,  G06F12/1009 ,  G06F15/167 ,  G06F9/445

Abstract: An apparatus includes a first processor to execute a user-level application to operate in a virtual address, and a co-processor to execute a computing kernel associated with user-level application elements to be performed on the co-processor. The computing kernel is to operate in the virtual address. A memory includes physical addresses, and a partition used to map the virtual address associated with the first processor and to map the virtual address associated with the co-processor. A packet processor manages communications between the first processor and the co-processor. The packet processor receives packets from the first processor, with the packets including memory addresses identifying code and data of the computing kernel. The packet processor stores the packets in a queue associated with the user-level application, and outputs the packets to the co-processor, such that the co-processor is enabled to execute the computing kernel.

公开(公告)号：US20210066271A1

公开(公告)日：2021-03-04

申请号：US17006092

申请日：2020-08-28

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Remi BRECHIGNAC ,  Jean-Michel RIVIERE

IPC: H01L25/16 ,  H01L33/62 ,  H01L31/02 ,  H01L31/0203 ,  H01L33/52

Abstract: An opaque dielectric carrier and confinement substrate is formed by a stack of layers laminated on each other. The stack includes a solid back layer and a front frame having a peripheral wall and an intermediate partition which delimits two cavities located on top of the solid back layer and on either side of the intermediate partition. Electronic integrated circuit (IC) chips are located inside the cavities and mounted on top of the solid back layer. Each IC chip includes an integrated optical element. Electrical connections are provided between the IC chips and back electrical contacts of the solid back layer. Transparent encapsulation blocks are molded in the cavities to embed the IC chips.

公开(公告)号：US10928843B2

公开(公告)日：2021-02-23

申请号：US16111933

申请日：2018-08-24

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Christophe Lorin

IPC: G05F1/46 ,  H02M1/10 ,  H02M7/04 ,  H03K5/00 ,  H02M1/00 ,  G06F13/38

Abstract: A device can be used for managing for managing the supply voltage on an output power supply pin of a USB Type-C source device that includes an AC-to-DC power converter for delivering the supply voltage. The source device is capable of supplying power to a receiver device. A power supply controller includes a first circuit configured to deliver a signal for discharging a capacitive network coupled to the power converter and also includes a second circuit configured to deliver, at the same time as the discharge signal, a new setpoint signal, corresponding to the new voltage delivered, to a control input of the power converter. A delay element is coupled between an output of the second circuit and the control input.

公开(公告)号：US10903388B2

公开(公告)日：2021-01-26

申请号：US16377379

申请日：2019-04-08

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jean-Michel Riviere

IPC: H01L31/167 ,  H01L31/02 ,  H01L23/00 ,  H01L31/0232 ,  G01V8/20 ,  H01L31/0203 ,  H01L25/16 ,  H01L31/173 ,  H01L25/065

Abstract: A main carrier wafer includes a first integrated network of electronic connections between front and back faces. A first electronic chip is mounted to the front face of the main carrier wafer and connected to the network of electronic connections of the main carrier wafer. A secondary carrier wafer includes a platform that extends over the first chip and a base the protrudes backwards with respect to the platform to a back end face facing the main wafer. A second integrated network of electronic connections is provided within the secondary carrier wafer. A second electronic chip is mounted on top of the platform and connected to the second integrated network. The second integrated network is further connected to the main carrier wafer at the back end face.

公开(公告)号：US10897822B2

公开(公告)日：2021-01-19

申请号：US16815554

申请日：2020-03-11

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Fabien Quercia ,  David Auchere ,  Norbert Chevrier ,  Fabien Corsat

IPC: H05K1/18 ,  H05K3/34

Abstract: A support substrate has first electric contacts in a front face. An electronic component is located above the front face of the support substrate and has second electric contacts facing the first electric contacts of the support substrate. An electric connection structure is interposed between corresponding first and second electric contacts of the support substrate and the electronic component, respectively. Each electric connection structure is formed by: a shim that is made of a first electrically conducting material, and a coating that is made of a second electrically conducting material (different from the first electrically conducting material). The coating surrounds the shim and is in contact with the corresponding first and second electric contacts of the support substrate and the electronic component.

公开(公告)号：US10862874B2

公开(公告)日：2020-12-08

申请号：US15939598

申请日：2018-03-29

Applicant: STMicroelectronics (Grenoble 2) SAS ,  TECHNOLOGICAL EDUCATIONAL INSTITUTE OF CRETE ,  Energica Motor Company S.p.A.

Inventor： Antonio-Marcello Coppola ,  Georgios Kornaros ,  Giovanni Gherardi

IPC: H04L29/06 ,  H04L29/08 ,  H04W4/48 ,  H04L12/417 ,  H04L9/08 ,  H04L9/14 ,  H04L9/30

Abstract: A CAN device is provided with an encryption function and a decryption function. The encryption function allows messages to be encrypted and put onto a CAN bus. The decryption function allows the messages on the CAN bus to be decrypted. The encryption and decryption functions share keys which change over the course of time.

公开(公告)号：US20200312735A1

公开(公告)日：2020-10-01

申请号：US16829210

申请日：2020-03-25

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Alexandre COULLOMB ,  Olivier FRANIATTE

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/373 ,  H01L23/49

Abstract: A substrate includes a through cavity. A heat sink is mounted so as to close one end of the through cavity. An integrated circuit (IC) chip is also mounted in the cavity. Conductive wires provide an electrical connection between pads on an upper surface of the IC chip and metallizations on the substrate. The mounted heat sink is positioned within the substrate in one implementation and positioned mounted to a back surface of the substrate in another implementation.