公开(公告)号：US07599218B2

公开(公告)日：2009-10-06

申请号：US11850510

申请日：2007-09-05

Applicant: Christophe Rodat ,  Thierry Giovinazzi

Inventor： Christophe Rodat ,  Thierry Giovinazzi

IPC: G11C16/04

CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2207/002 ,  G11C2213/79

Abstract: An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory cells, a second device supplying a second voltage applicable to memory cells. Each memory cell selection block includes a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device. The first sub-block includes MOS transistors of a first type of conductivity, and the second sub-block includes MOS transistors of a second type of conductivity. Application may be particularly but not exclusively to phase change memories.

Abstract translation: 集成电路包括具有存储单元的非易失性存储器，具有选择块的存储单元选择电路，提供适用于存储单元的第一电压的第一器件，提供适用于存储器单元的第二电压的第二器件。 每个存储器单元选择块包括用于将存储器单元链接到第一设备的第一选择子块和将存储器单元链接到第二设备的第二选择子块。 第一子块包括具有第一类导电性的MOS晶体管，第二子块包括第二导电类型的MOS晶体管。 应用可以特别地但不排他地用于相变存储器。

公开(公告)号：US07598876B2

公开(公告)日：2009-10-06

申请号：US11385458

申请日：2006-03-21

Applicant: Sylvain Fidelis ,  Pierre Rizzo

Inventor： Sylvain Fidelis ,  Pierre Rizzo

IPC: G08B13/14

CPC classification number: G06K19/07749 ,  G06K19/07718 ,  G06K19/07758 ,  H01L2224/16 ,  H01L2924/10253 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method for manufacturing an electronic tag to be affixed onto a product includes providing, in an electrically conductive film of a foil for packaging, packing or transporting the product, areas devoid of any electrically conductive material for delimiting in the electrically conductive film at least one antenna pattern for forming an antenna for an RFID tag. A semiconductor chip is connected to the antenna for forming an electronic tag.

Abstract translation: 用于制造要贴在产品上的电子标签的方法包括在用于包装，包装或运输产品的箔的导电膜中提供没有任何导电材料的区域，用于在导电膜中限定至少一个 用于形成用于RFID标签的天线的天线方向图。 半导体芯片连接到用于形成电子标签的天线。

公开(公告)号：US07598145B2

公开(公告)日：2009-10-06

申请号：US11761074

申请日：2007-06-11

Applicant: Jean-Francois Damlencourt ,  Yves Morand ,  Laurent Clavelier

Inventor： Jean-Francois Damlencourt ,  Yves Morand ,  Laurent Clavelier

IPC: H01L21/336

CPC classification number: H01L21/32105 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78684

Abstract: A method for producing a microelectronic device comprising a plurality of Si1-yGey based semi-conductor zones (wherein 0

Abstract translation: 一种微电子器件的制造方法，该微电子器件包括具有不同锗锗含量的多个Si 1-y Ga y基半导体区（其中0

公开(公告)号：US07589411B2

公开(公告)日：2009-09-15

申请号：US11305886

申请日：2005-12-16

Applicant: Pierre Bormann ,  Luc Morineau ,  Jacques Chavade

Inventor： Pierre Bormann ,  Luc Morineau ,  Jacques Chavade

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/49838 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/10734

Abstract: A device is provided for electrically connecting an integrated circuit chip. The device includes a main board, an intermediate board, and electrical connection balls in a space separating the boards. In the space, a peripheral zone comprises a peripheral matrix of balls, a central zone comprises a central matrix of balls, a first secondary zone comprises a matrix of electrical connection vias linked to the balls of the two adjacent rows of balls of the peripheral matrix, and a second secondary zone comprises a matrix of electrical connection vias linked to balls of the central matrix. The first secondary zone and the second secondary zone are separated by an intermediate zone that includes at least a first part having at least one complementary row of electrical connection balls, and a second part having complementary electrical connection vias linked to the balls of this complementary row.

Abstract translation: 提供一种用于电连接集成电路芯片的装置。 该装置包括主板，中间板和分隔板的空间中的电连接球。 在该空间中，周边区域包括球的外围矩阵，中心区域包括球的中心矩阵，第一次级区域包括连接到外围矩阵的两个相邻行球的球的电连接通孔矩阵 ，并且第二次级区域包括连接到中心矩阵的球的电连接通孔矩阵。 第一次级区域和第二次级区域由包括至少一个具有至少一个互补排的电连接球的第一部分的中间区隔开，以及具有互补电连接通路的第二部分，该互补电连接通孔连接到该互补排的球 。

公开(公告)号：US07577401B2

公开(公告)日：2009-08-18

申请号：US11040169

申请日：2005-01-19

Applicant: Jean-Yves Couet

Inventor： Jean-Yves Couet

IPC: H04B7/185

CPC classification number: H04H40/90 ,  H04N7/104

Abstract: A system and method for signal distribution within a satellite reception installation. The system includes a receiver for receiving a satellite signal, and for selecting an external signal from among several external signals included in the satellite signal. The signal selected is pre-processed. A plurality of processing units are each linked to the receiver via a respective associated wire link and operating in reception in the UHF frequency band called Satellite Intermediate Band (SIB) and a signal distribution subsystem with a switching matrix for switching the pre-processed selected external signal to at least one of the processing units via the associated wire link. The signal distribution subsystem further includes at least one connection internal to the satellite reception installation, adapted for the transmission of an internal signal which is transmitted in the SIB by a first processing unit selected from the plurality of processing units to at least one second processing unit selected from the plurality of processing units, via the signal distribution subsystem.

Abstract translation: 卫星接收设备内信号分配的系统和方法。 该系统包括用于接收卫星信号的接收器，并用于从包括在卫星信号中的多个外部信号中选择外部信号。 选择的信号是预处理的。 多个处理单元各自经由相应的相关联的线路链接到接收机，并且在被称为卫星中间频带（SIB）的UHF频带中的接收中操作，以及信号分配子系统，具有用于切换预处理的所选择的外部 通过相关联的线路链接到至少一个处理单元。 所述信号分配子系统还包括所述卫星接收设备内部的至少一个连接，所述至少一个连接适用于通过由所述多个处理单元中选择的第一处理单元在所述SIB中发送的至少一个第二处理单元 通过信号分配子系统从多个处理单元中选择。

公开(公告)号：US20090167261A1

公开(公告)日：2009-07-02

申请号：US12336518

申请日：2008-12-16

Applicant: Severin TROCHUT

Inventor： Severin TROCHUT

IPC: G05F1/10 ,  G01R19/00

CPC classification number: H02M3/1588 ,  G01R19/0092 ,  H02M2001/0009 ,  Y02B70/1466

Abstract: An embodiment of a current measuring device, defined by a gain, including an amplification module including an input for receiving a control signal, an input connected to an output node, brought to an output potential and traversed by an output current, a feedback node traversed by a mirror current associated with the output current by a proportionality coefficient equal to the gain, and an output traversed by the mirror current, and capable of bringing the feedback node to the output potential in response to the control signal. The measuring device also includes a gain modification module, mounted between the first potential and the feedback node, including at least one input for receiving an activation signal, and capable of modifying the value of the gain in response to an activation signal.

Abstract translation: 由增益定义的电流测量装置的实施例，包括放大模块，该放大模块包括用于接收控制信号的输入，连接到输出节点的输入，输出到输出电位并被输出电流穿过;反馈节点 通过与输出电流相关联的镜像电流等于增益的比例系数，以及由镜电流穿过的输出，并且能够响应于控制信号使反馈节点进入输出电位。 测量装置还包括安装在第一电势和反馈节点之间的增益修改模块，包括用于接收激活信号的至少一个输入，并且能够响应于激活信号修改增益的值。

公开(公告)号：US07549109B2

公开(公告)日：2009-06-16

申请号：US11301635

申请日：2005-12-13

Applicant: Michel Harrand

Inventor： Michel Harrand

IPC: G11C29/00

CPC classification number: G11C7/1075 ,  G06F11/1008 ,  G06F12/0893 ,  G06F2212/3042 ,  G11C8/16 ,  G11C2207/2245

Abstract: A dual port memory circuit has a memory plane including first and second modules each constituted of an array of memory cells arranged in columns and rows, each row of the memory plane allowing storage of a page of words, each word of the page being identified by an address organized according to a hierarchical division defined by (@MSB, row address, column address), with @MSB identifying a particular module among the n modules. The circuit comprises first and second address buses, and first and second data buses used for reading and writing the modules, respectively. For each memory module, there is provided a multiplexer having two inputs connected to both address buses. The multiplexer output is connected to a row decoder and to first and second column decoders corresponding to the first and second data buses. Each multiplexer is controlled to allow writing and simultaneous reading of two distinct modules.

Abstract translation: 双端口存储器电路具有包括第一和第二模块的存储器平面，每个模块由以列和行排列的存储器单元的阵列构成，存储器平面的每一行允许存储一页单词，页面的每个单词由 根据由（@MSB，行地址，列地址）定义的分层划分组织的地址，其中@MSB标识n个模块中的特定模块。 该电路包括分别用于读取和写入模块的第一和第二地址总线以及第一和第二数据总线。 对于每个存储器模块，提供了具有连接到两个地址总线的两个输入的多路复用器。 复用器输出连接到行解码器和对应于第一和第二数据总线的第一和第二列解码器。 每个复用器被控制以允许写入和同时读取两个不同的模块。

公开(公告)号：US07531447B2

公开(公告)日：2009-05-12

申请号：US11220353

申请日：2005-09-06

Applicant: Pierre Caubet ,  Magali Gregoire

Inventor： Pierre Caubet ,  Magali Gregoire

IPC: H01L23/538

CPC classification number: H01L21/76838 ,  H01L21/76877 ,  H01L23/53228 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% crystal orientation and a less than 20% crystal orientation.

Abstract translation: 集成电路包括铜线，其中铜的晶体结构具有大于30％的<001>晶体取向和小于20％的<111>晶体取向。

公开(公告)号：US07523259B2

公开(公告)日：2009-04-21

申请号：US10926778

申请日：2004-08-26

Applicant: Pierre Pistoulet

Inventor： Pierre Pistoulet

IPC: G66F13/18

CPC classification number: G06F12/1425 ,  G06F12/0875 ,  Y02D10/13

Abstract: A cache memory includes a memory array comprising logic latches, and a circuit for reading the cache memory arranged for receiving a reference tag at input, comparing tags present in the cache memory relative to the reference tag and, if a tag is identical to the reference tag, selecting the source datum associated with the identical tag. A device for controlling access to a data memory includes a storage unit that stores a plurality of attributes defining rights of access to the data memory, the cache memory, and a synchronous attribute search circuit, for searching for an attribute in the storage unit if the attribute is not in the cache memory.

Abstract translation: 高速缓存存储器包括包括逻辑锁存器的存储器阵列和用于读取设置用于在输入处接收参考标签的高速缓冲存储器的电路，比较高速缓冲存储器中相对于参考标签存在的标签，以及如果标签与参考标记相同 标签，选择与相同标签相关联的源数据。 用于控制对数据存储器的访问的设备包括存储单元，其存储定义对数据存储器，高速缓冲存储器和同步属性搜索电路的访问权限的多个属性，用于在存储单元中搜索属性，如果 属性不在缓存中。

公开(公告)号：US20090089347A1

公开(公告)日：2009-04-02

申请号：US11653185

申请日：2007-01-12

Applicant: Alain Pomet ,  Benjamin Duval ,  Robert Leydier

Inventor： Alain Pomet ,  Benjamin Duval ,  Robert Leydier

IPC: G06F7/58

CPC classification number: G06F7/588

Abstract: A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.

Abstract translation: 一种用于产生随机数的方法，包括以下步骤：接收经历相位抖动的数据传输二进制信号，产生基本上具有相同平均频率的几个振荡器信号，并具有不同的相位，在出现时对每个振荡器信号的状态进行采样 的二进制信号的边沿，并且使用每个振荡器信号的状态来产生随机数。 该方法可以应用于可用于智能卡的集成电路。