公开(公告)号：US20120139605A1

公开(公告)日：2012-06-07

申请号：US13308478

申请日：2011-11-30

Applicant: Chung-Chang Lin

Inventor： Chung-Chang Lin

IPC: H03L5/00

CPC classification number: H03K19/0008

Abstract: An integrated circuit includes: a circuit pin; a detecting circuit coupled to the circuit pin, and arranged to detect a signal level value of the circuit pin when the integrated circuit operates in a first operational mode; a storage circuit coupled to the detecting circuit, and arranged to store the signal level value; and a controlling circuit coupled to the storage circuit, and arranged to set a voltage level of the circuit pin according the signal level value when a processing circuit of the integrated circuit operates in a second operational mode.

Abstract translation: 集成电路包括：电路引脚; 检测电路，其耦合到所述电路引脚，并且被布置成当所述集成电路在第一操作模式下操作时检测所述电路引脚的信号电平值; 存储电路，耦合到所述检测电路，并且被布置成存储所述信号电平值; 以及控制电路，其耦合到所述存储电路，并且被布置成当所述集成电路的处理电路在第二操作模式下操作时，根据所述信号电平值来设置所述电路引脚的电压电平。

公开(公告)号：US08193895B2

公开(公告)日：2012-06-05

申请号：US12827205

申请日：2010-06-30

Applicant: Tsung-Hsiao Wu ,  Ching-Hsien Teng ,  Kao-Tsai Liao ,  Zhi-Liang Zhang ,  Tian-Chang Lin ,  Ming Yeh

Inventor： Tsung-Hsiao Wu ,  Ching-Hsien Teng ,  Kao-Tsai Liao ,  Zhi-Liang Zhang ,  Tian-Chang Lin ,  Ming Yeh

IPC: H01F27/30 ,  H01F5/00 ,  H01F7/06

CPC classification number: H05K1/0233 ,  H01F17/062 ,  H01F27/2804 ,  H01F27/2847 ,  H01F2027/2814 ,  H05K1/141 ,  H05K1/18 ,  H05K2201/086 ,  H05K2201/09027 ,  Y10T29/4902 ,  Y10T29/49124

Abstract: A magnetic assembly includes a magnetic core, a circuit board and multiple conductive elements. The circuit board includes multiple conductive regions. The conductive elements stride over the magnetic core. Each of the conductive elements includes a first terminal, a second terminal and a connecting part. The connecting part is arranged between the first terminal and the second terminal for connecting the first terminal with the second terminal. The first terminal and the second terminal of each conductive element are respectively connected to two adjacent conductive regions. The multiple conductive elements and the multiple conductive regions collectively define multiple loops. The multiple loops interact with the magnetic core to generate inductance.

Abstract translation: 磁性组件包括磁芯，电路板和多个导电元件。 电路板包括多个导电区域。 导电元件跨越磁芯。 每个导电元件包括​​第一端子，第二端子和连接部件。 连接部分布置在第一端子和第二端子之间，用于将第一端子与第二端子连接。 每个导电元件的第一端子和第二端子分别连接到两个相邻的导电区域。 多个导电元件和多个导电区域共同限定多个环路。 多个环路与磁芯相互作用以产生电感。

公开(公告)号：US08172617B2

公开(公告)日：2012-05-08

申请号：US12753493

申请日：2010-04-02

Applicant: Chang Lin Peng

Inventor： Chang Lin Peng

IPC: H01R13/66

CPC classification number: H01R24/44 ,  H01R2103/00 ,  Y10S439/944

Abstract: A radio-frequency connector consisting of a socket member and a plug member electrically connectable to the socket member is disclosed. The socket member or plug member has an impedance element mounted therein such that the impedance element is electrically connected to the metal casing and metal center pin of the socket member or plug member that carries the impedance element when the plug member is disconnected from the socket member, causing the impedance element to provide a terminal effect to insolate external electromagnetic noises; the impedance element is separated from the metal casing and metal center pin of the socket member or plug member that carries impedance element when the plug member is connected to the socket member.

Abstract translation: 公开了一种射频连接器，其由插座构件和可与插座构件电连接的插头构件组成。 插座构件或插头构件具有安装在其中的阻抗元件，使得阻抗元件电连接到当插头构件与插座构件断开时承载阻抗元件的插座构件或插头构件的金属外壳和金属中心销 ，使阻抗元件提供端接效应，以使外部电磁噪声不必要; 当插头构件连接到插座构件时，阻抗元件与承载阻抗元件的插座构件或插头构件的金属外壳和金属中心销分开。

公开(公告)号：US20120040504A1

公开(公告)日：2012-02-16

申请号：US12853450

申请日：2010-08-10

Applicant: HSIN CHANG LIN ,  CHIA-HAO TAI ,  YANG-SEN YEN ,  MING-TSANG YANG ,  YA-TING FAN

Inventor： HSIN CHANG LIN ,  CHIA-HAO TAI ,  YANG-SEN YEN ,  MING-TSANG YANG ,  YA-TING FAN

IPC: H01L21/8246

CPC classification number: H01L27/105 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526

Abstract: The present invention discloses a method for integrating DRAM and NVM, which comprises steps: sequentially forming on a portion of surface of a DRAM semiconductor substrate a first gate insulation layer and a first gate layer functioning as a floating gate; and implanting ion into regions of the semiconductor substrate, which are at two sides of the first gate insulation layer, to form two heavily-doped areas that are adjacent to the first gate insulation layer and respectively function as a drain and a source; respectively forming over the first gate layer a second gate insulation layer and a second gate layer functioning as a control gate. The present invention not only increases the transmission speed but also reduces the power consumption, the fabrication cost and the package cost.

Abstract translation: 本发明公开了一种用于整合DRAM和NVM的方法，包括以下步骤：在DRAM半导体衬底的表面的一部分上依次形成第一栅极绝缘层和用作浮动栅极的第一栅极层; 以及将离子注入位于所述第一栅极绝缘层两侧的半导体衬底的区域中，以形成与所述第一栅极绝缘层相邻并分别用作漏极和源极的两个重掺杂区域; 分别在第一栅极层上形成第二栅极绝缘层和用作控制栅极的第二栅极层。 本发明不仅提高了传输速度，而且降低了功耗，制造成本和封装成本。

公开(公告)号：US20120032731A1

公开(公告)日：2012-02-09

申请号：US12849503

申请日：2010-08-03

Applicant: Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Chih-Chang LIN ,  Tien-Chun YANG ,  Yuwen SWEI

Inventor： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Chih-Chang LIN ,  Tien-Chun YANG ,  Yuwen SWEI

IPC: G05F3/02 ,  H01L25/00

CPC classification number: H02M3/07

Abstract: An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.

Abstract translation: 集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。 第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。 集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。

公开(公告)号：US08111756B2

公开(公告)日：2012-02-07

申请号：US11512287

申请日：2006-08-30

Applicant: Jiun-In Guo ,  Jinn-Shyan Wang ,  Jia-Wei Chen ,  Chun-Hao Chang ,  Yi-Huan Ou Yang ,  Chien-Chang Lin

Inventor： Jiun-In Guo ,  Jinn-Shyan Wang ,  Jia-Wei Chen ,  Chun-Hao Chang ,  Yi-Huan Ou Yang ,  Chien-Chang Lin

IPC: H04N7/12

CPC classification number: H04N19/11 ,  H04N19/176

Abstract: A method for reducing computational complexity of video compression standard is provided, and it includes an intra 4×4 macroblock (I4MB) search algorithm, an intra 16×16 macroblock (I16MB) search algorithm and a chroma search algorithm. The I4MB search algorithm and I16MB search algorithm accelerate the prediction process of the luma macroblock, and the chroma search algorithm accelerates the prediction process of chroma macroblock. The above algorithms can greatly reduce the computation of prediction mode of video compression standard.

Abstract translation: 提供了一种降低视频压缩标准计算复杂度的方法，包括内部4×4宏块（I4MB）搜索算法，帧内16×16宏块（I16MB）搜索算法和色度搜索算法。 I4MB搜索算法和I16MB搜索算法加速了亮度宏块的预测过程，色度搜索算法加速了色度宏块的预测过程。 上述算法可以大大减少视频压缩标准预测模式的计算。

公开(公告)号：US08111291B2

公开(公告)日：2012-02-07

申请号：US12248230

申请日：2008-10-09

Applicant: Kun-Chi Liao ,  Yi-Chang Lin

Inventor： Kun-Chi Liao ,  Yi-Chang Lin

IPC: H04N17/00 ,  H04N5/20

CPC classification number: H04N5/23248 ,  H04N5/23254 ,  H04N5/2327 ,  H04N5/243

Abstract: Image capture systems capable of ensuring clear images are provided, in which an image capture module senses at least one image, and an operational module performs a compensation to the image capture system according to a modulation transfer function (MTF) value corresponding to the image, such that the image capture system can be operated under an optimized total gain thereby ensuring clear images.

Abstract translation: 提供能够确保清晰图像的图像捕获系统，其中图像捕获模块感测至少一个图像，并且操作模块根据与图像对应的调制传递函数（MTF）值对图像捕获系统执行补偿， 使得图像捕获系统可以在优化的总增益下操作，从而确保清晰的图像。

公开(公告)号：US20120019154A1

公开(公告)日：2012-01-26

申请号：US12880161

申请日：2010-09-13

Applicant: Chien-Yang Chen ,  Po-Kun Hsieh ,  Tung-Hsin Lan ,  Ming-Chang Lin

Inventor： Chien-Yang Chen ,  Po-Kun Hsieh ,  Tung-Hsin Lan ,  Ming-Chang Lin

IPC: H05B37/02 ,  H05B41/16

CPC classification number: H05B33/0818 ,  H05B33/0848

Abstract: A power supply unit provides a voltage, and a driving current to a series of light emitting diodes. A dimming unit adjusts a duty cycle of an original dimming signal to generate a dimming signal according to the driving current and an ideal current. A current sink coupled to the series of light emitting diodes adjusts a duty cycle of the driving current according to the dimming signal.

Abstract translation: 电源单元向一系列发光二极管提供电压和驱动电流。 调光单元调节原始调光信号的占空比，根据驱动电流和理想电流产生调光信号。 耦合到一系列发光二极管的电流吸收器根据调光信号来调节驱动电流的占空比。

公开(公告)号：US20120013374A1

公开(公告)日：2012-01-19

申请号：US12835130

申请日：2010-07-13

Applicant: Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

Inventor： Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

IPC: H03L7/06

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.

Abstract translation: 一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。

公开(公告)号：US20120012203A1

公开(公告)日：2012-01-19

申请号：US12838493

申请日：2010-07-18

Applicant: Chen-Chang Lin

Inventor： Chen-Chang Lin

IPC: F16K21/00

CPC classification number: E03C1/0404 ,  A47K1/00 ,  A47K1/09 ,  Y10T137/8376 ,  Y10T137/87539

Abstract: The water tap has a tap stand and a storage frame. The tap stand is has a flowing channel formed through the tap stand. The storage frame is mounted on the tap stand and has a flowing groove and a storage hole. The flowing groove is annular and formed in a top surface of the storage frame and communicates with the flowing channel of the tap stand. The storage hole is formed through the storage frame to provide a storage function.

Abstract translation: 水龙头有一个水龙头架和一个储物架。 龙头架具有通过龙头架形成的流动通道。 存储框架安装在水龙头架上，并具有流动的槽和存储孔。 流动的槽是环形的并且形成在存储框架的顶表面中，并与抽头支架的流动通道连通。 存储孔通过存储框架形成以提供存储功能。