公开(公告)号：US07816744B2

公开(公告)日：2010-10-19

申请号：US12170133

申请日：2008-07-09

Applicant: Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

Inventor： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC: H01L29/49

CPC classification number: H01L29/4983 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

Abstract translation: 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。 栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。 第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

公开(公告)号：US20100096697A1

公开(公告)日：2010-04-22

申请号：US12256009

申请日：2008-10-22

Applicant: Ru-Yi Su ,  Pou-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun Lin Tsai ,  Chien-Chih Chou

Inventor： Ru-Yi Su ,  Pou-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun Lin Tsai ,  Chien-Chih Chou

IPC: H01L29/78

CPC classification number: H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7835

Abstract: A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other.

Abstract translation: 半导体器件包括半导体衬底，形成在衬底中的源极区和漏极区，形成在衬底上的栅极结构，该衬底设置在源极和漏极区之间，第一隔离结构形成在栅极结构和栅极结构之间的衬底中 漏极区域，所述第一隔离结构包括位于所述漏极区域的边缘附近的突起。 每个突起包括在沿着漏极区域的边缘的第一方向上测量的宽度和在垂直于第一方向的第二方向上测量的长度，并且相邻的突起彼此间隔一定距离。

公开(公告)号：US20060205232A1

公开(公告)日：2006-09-14

申请号：US11076702

申请日：2005-03-10

Applicant: Lih-Ping Li ,  Tzong-Sheng Chang ,  William Kuo ,  Tsung-Hsien Lee ,  Chun-Lin Tsai ,  Szu-An Wu ,  Yin-Ping Lee

Inventor： Lih-Ping Li ,  Tzong-Sheng Chang ,  William Kuo ,  Tsung-Hsien Lee ,  Chun-Lin Tsai ,  Szu-An Wu ,  Yin-Ping Lee

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/0276 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828

Abstract: A method for etching a dielectric material in a semiconductor device is disclosed. After providing a conductive region, a dielectric layer is formed over the conductive region. A dielectric antireflective coating (DARC) layer is further formed on the dielectric layer. Then, a moisture-removal step is performed that removes moisture from the DARC layer and from an interface region between the dielectric and the DARC layer. A masking pattern is transferred into the DARC layer and the dielectric layer.

Abstract translation: 公开了一种在半导体器件中蚀刻介电材料的方法。 在提供导电区域之后，在导电区域上形成电介质层。 在电介质层上进一步形成电介质抗反射涂层（DARC）层。 然后，进行除湿步骤，其从DARC层和电介质层与DARC层之间的界面区域去除水分。 掩模图案被传送到DARC层和电介质层。

公开(公告)号：US06847061B2

公开(公告)日：2005-01-25

申请号：US10406120

申请日：2003-04-03

Applicant: Chun-Lin Tsai ,  Denny D. Tang ,  Chih-Min Chiang ,  Kuan-Lun Chang ,  Tsyr Shyang ,  Ruey-Hsin Liu

Inventor： Chun-Lin Tsai ,  Denny D. Tang ,  Chih-Min Chiang ,  Kuan-Lun Chang ,  Tsyr Shyang ,  Ruey-Hsin Liu

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/737 ,  H01L31/0328 ,  H01L31/072

CPC classification number: H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

Abstract: During the conventional manufacture of HBTs, implant damage occurs which leads to enhanced internal base diffusion. This problem has been overcome by making the base and base contact area from a single, uniformly doped layer of silicon-germanium. Instead of an ion implant step to selectively reduce the resistance of this layer away from the base, a layer of polysilicon is selectively deposited (using selective epi deposition) onto only that part. Additionally, the performance of the polysilicon emitter is enhanced by means a brief thermal anneal that drives a small amount of opposite doping type silicon into the SiGe base layer.

Abstract translation: 在常规制造HBT期间，会发生植入物损伤，导致内部基极扩散增强。 通过从单个均匀掺杂的硅 - 锗层制造基极和基极接触面积已经克服了该问题。 代替离子注入步骤来选择性地降低该层离开基极的电阻，选择性地沉积多晶硅层（使用选择性epi沉积）到该部分上。 此外，多晶硅发射极的性能通过将少量相反掺杂型硅驱动到SiGe基极层中的短暂的热退火来增强。

公开(公告)号：US06703282B1

公开(公告)日：2004-03-09

申请号：US10187708

申请日：2002-07-02

Applicant: Fu Ji Yang ,  Chun Lin Tsai ,  Chien Chih Chou ,  Ting Jia Hu ,  Sheng Yuan Lin

Inventor： Fu Ji Yang ,  Chun Lin Tsai ,  Chien Chih Chou ,  Ting Jia Hu ,  Sheng Yuan Lin

IPC: H01L21336

CPC classification number: H01L29/6656 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185

Abstract: A method of forming an NMOS device with reduced device degradation, generated during a constant current stress, has been developed. The reduced device degradation is attributed to the use of a high temperature oxide (HTO), layer, used as an underlying component of composite insulator spacers, formed on the sides of the NMOS gate structures. After definition of an insulator capped polycide gate structure a thin, (140 to 160 Angstrom), HTO layer is deposited at a temperature between about 700 to 800° C., followed by the deposition of a silicon nitride layer. Definition of the composite insulator layer, comprised with the underlying, HTO, results in NMOS devices with reduced drain current and reduced transconductance values, when compared to counterparts fabricated with composite insulator spacers formed without the thin, HTO layer featured in this invention.

Abstract translation: 已经开发了在恒定电流应力期间产生的具有降低的器件劣化的NMOS器件的形成方法。 降低的器件劣化归因于使用形成在NMOS栅极结构的侧面上的用作复合绝缘体间隔物的潜在部件的高温氧化物（HTO）层。 在绝缘体封端的多晶硅栅极结构的定义之后，在约700至800℃之间的温度下沉积薄（140至160埃）的HTO层，随后沉积氮化硅层。 与底层的HTO组成的复合绝缘体层的定义导致具有降低的漏极电流和降低的跨导值的NMOS器件与在不具有本发明特征的薄HTO层的复合绝缘体间隔物制造的对应物上相比。