公开(公告)号：US20110038218A1

公开(公告)日：2011-02-17

申请号：US12911173

申请日：2010-10-25

Applicant: Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

Inventor： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

IPC: G11C29/08

CPC classification number: G11C29/022 ,  G11C29/02

Abstract: A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

Abstract translation: 提供了一种存储芯片及其操作方法。 存储器芯片包括多个焊盘。 该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。

公开(公告)号：US20100202213A1

公开(公告)日：2010-08-12

申请号：US12767418

申请日：2010-04-26

Applicant: Yung-Feng Lin ,  Chun-Yi Lee

Inventor： Yung-Feng Lin ,  Chun-Yi Lee

IPC: G11C16/06 ,  G11C7/06

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C7/08 ,  G11C16/28 ,  G11C2207/063

Abstract: A sense amplifying method, applied in a memory having a memory cell and a reference cell, includes: charging the memory cell and the reference cell to have a cell current and a reference current, respectively; duplicating the cell current and the reference current to respectively generate a mirrored cell current via a first current path and a mirrored reference current via a second current path and equalizing a first voltage drop generated as the mirrored cell current flows by the first current path and a second voltage drop generated as the mirrored reference current flows by the second current path; and removing the equalization of the first voltage drop and the second voltage drop and adjusting first voltage drop and the second voltage drop according to a first current flowing by the first current path and a second current flowing by the second current path.

Abstract translation: 应用于具有存储单元和参考单元的存储器中的感测放大方法包括：分别对存储单元和参考单元充电以具有单元电流和参考电流; 复制单元电流和参考电流以经由第二电流路径分别经由第一电流路径和镜像参考电流产生镜像单元电流，并且均衡由第一电流路径流动的镜像单元电流产生的第一电压降和 当第二电流路径流过镜像参考电流时产生的第二电压降; 以及去除所述第一电压降和所述第二电压降的均衡，并且根据由所述第一电流路径流动的第一电流和由所述第二电流路径流动的第二电流来调节第一电压降和所述第二电压降。

公开(公告)号：US07750416B2

公开(公告)日：2010-07-06

申请号：US11416938

申请日：2006-05-03

Applicant: Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

Inventor： Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

IPC: H01L29/76

CPC classification number: H01L27/0883 ,  G11C11/412 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S438/919

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract translation: 提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在 源极/漏极区域。 上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

公开(公告)号：US20090295419A1

公开(公告)日：2009-12-03

申请号：US12256042

申请日：2008-10-22

Applicant: Kuen-Long CHANG ,  Chun-Hsiung HUNG ,  Chuan-Ying YU ,  Chun-Yi LEE

Inventor： Kuen-Long CHANG ,  Chun-Hsiung HUNG ,  Chuan-Ying YU ,  Chun-Yi LEE

IPC: G01R31/3187

CPC classification number: G11C29/022 ,  G11C29/02

Abstract: A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

Abstract translation: 提供了一种存储芯片及其操作方法。 存储器芯片包括多个焊盘。 该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。

公开(公告)号：US20060230316A1

公开(公告)日：2006-10-12

申请号：US11095720

申请日：2005-03-30

Applicant: Ying-Chih Lu ,  Meng-Hua Cheng ,  Chun-Yi Lee ,  Lung-Hung Yu ,  Chi-Tsung Chang ,  Chia-Hsing Lee

Inventor： Ying-Chih Lu ,  Meng-Hua Cheng ,  Chun-Yi Lee ,  Lung-Hung Yu ,  Chi-Tsung Chang ,  Chia-Hsing Lee

IPC: G06F11/00

CPC classification number: G06F11/1417

Abstract: A method for ensuring normal operation at an Early Power-On Self Test stage of a computer device is proposed. The method is applied to the computer devices having a timing function. A largest execution time for at least an Early POST program is preset, and the actual execution time of the Early POST program is counted when the computer device is activated. If the execution time of the POST program is greater than the largest execution time, the computer devices will then be restarted, the POST program will be re-executed, and the timing process of the POST program will be performed again, until execution time of every Early POST programs is smaller or equal to the corresponding preset largest execution time. Upon which, the timing will be terminated, and the computer devices will be able to enter into the stage of Later POST. This method ensures any Early POST program causing the system to hang to be cleared by automatically restarting the computer system, so that users will not experience system hangs during the Early POST stage.

Abstract translation: 提出了一种在计算机设备的早期开机自检阶段确保正常运行的方法。 该方法应用于具有定时功能的计算机设备。 预设至少一个Early POST程序的最大执行时间，并且在启动计算机设备时计算Early POST程序的实际执行时间。 如果POST程序的执行时间大于最大执行时间，则计算机设备将重新启动，POST程序将被重新执行，POST程序的定时处理将再次执行，直到执行时间 每个早期POST程序小于或等于相应的预设最大执行时间。 计时器将被终止，计算机设备将进入后期POST阶段。 此方法确保任何早期POST程序导致系统挂起以通过自动重新启动计算机系统来清除，以便用户在早期POST阶段不会遇到系统挂起。

公开(公告)号：US20060230196A1

公开(公告)日：2006-10-12

申请号：US11096325

申请日：2005-03-30

Applicant: Ying-Chih Lu ,  Meng-Hua Cheng ,  Chun-Yi Lee ,  Lung-Hung Yu ,  Chun-Lung Wu ,  Chia-Hsing Lee

Inventor： Ying-Chih Lu ,  Meng-Hua Cheng ,  Chun-Yi Lee ,  Lung-Hung Yu ,  Chun-Lung Wu ,  Chia-Hsing Lee

IPC: G06F3/00

CPC classification number: G06F11/0766 ,  G06F11/0748 ,  G06F11/3055 ,  G06F11/3058 ,  G06F11/3065

Abstract: A monitoring system and method utilizing System Management Interrupt is proposed. The monitoring system is applicable to electronic facilities for monitoring and recording operational status of the electronic facilities. According to the operational status, the electronic facility generates System Management Interrupt (SMI) related data, and execute a specific program (a SMI Handler) stored in a first data storage area of the data storage unit that allows the SMI related data to be stored in a second data storage area of the data storage unit. Base on the stored SMI related data, a system software tester will be able to analyze abnormal situations occurred in the electronic facilities.

Abstract translation: 提出了利用系统管理中断的监控系统和方法。 监控系统适用于监控和记录电子设备运行状况的电子设备。 根据操作状态，电子设备生成系统管理中断（SMI）相关数据，并且执行存储在数据存储单元的第一数据存储区域中的特定程序（SMI处理程序），其允许存储SMI相关数据 在数据存储单元的第二数据存储区域中。 基于存储的SMI相关数据，系统软件测试人员将能够分析电子设备中发生的异常情况。

公开(公告)号：US06893909B2

公开(公告)日：2005-05-17

申请号：US10681768

申请日：2003-10-07

Applicant: Yu-Ren Wang ,  Chun-Yi Lee ,  Yu-Kun Chen ,  Neng-Hui Yang

Inventor： Yu-Ren Wang ,  Chun-Yi Lee ,  Yu-Kun Chen ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/265 ,  H01L21/28035 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of manufacturing a MOS transistor is provided. A gate insulation layer and a conductive layer are sequentially formed over a substrate. A pre-amorphization implantation is carried out to amorphize the conductive layer. The conductive layer and the gate insulation layer are patterned to form a gate structure. A first spacer is formed on the sidewall of the gate structure. A second pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer and then a doped source/drain region is formed in the substrate on each side of the second spacer. A solid phase epitaxial process is carried out to convert the doped source/drain extension region and the doped source/drain region into a source/drain terminal. In the pre-amorphization implantations, dopants having an ionic radius greater than the germanium ion are used.

Abstract translation: 提供一种制造MOS晶体管的方法。 栅极绝缘层和导电层依次形成在衬底上。 进行前非晶化注入以使导电层非晶化。 将导电层和栅极绝缘层图案化以形成栅极结构。 在栅极结构的侧壁上形成第一间隔物。 进行第二次非晶化植入以使基板的一部分非晶化。 在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。 在第一间隔物的侧壁上形成第二间隔物，然后在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。 进行固相外延处理以将掺杂的源极/漏极延伸区域和掺杂的源极/漏极区域转换成源极/漏极端子。 在前非晶化注入中，使用离子半径大于锗离子的掺杂剂。

公开(公告)号：US20050074931A1

公开(公告)日：2005-04-07

申请号：US10681768

申请日：2003-10-07

Applicant: Yu-Ren Wang ,  Chun-Yi Lee ,  Yu-Kun Chen ,  Neng-Hui Yang

Inventor： Yu-Ren Wang ,  Chun-Yi Lee ,  Yu-Kun Chen ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/265 ,  H01L21/28035 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of manufacturing a MOS transistor is provided. A gate insulation layer and a conductive layer are sequentially formed over a substrate. A pre-amorphization implantation is carried out to amorphize the conductive layer. The conductive layer and the gate insulation layer are patterned to form a gate structure. A first spacer is formed on the sidewall of the gate structure. A second pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer and then a doped source/drain region is formed in the substrate on each side of the second spacer. A solid phase epitaxial process is carried out to convert the doped source/drain extension region and the doped source/drain region into a source/drain terminal. In the pre-amorphization implantations, dopants having an ionic radius greater than the germanium ion are used.

Abstract translation: 提供一种制造MOS晶体管的方法。 栅极绝缘层和导电层依次形成在衬底上。 进行前非晶化注入以使导电层非晶化。 将导电层和栅极绝缘层图案化以形成栅极结构。 在栅极结构的侧壁上形成第一间隔物。 进行第二次非晶化植入以使基板的一部分非晶化。 在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。 在第一间隔物的侧壁上形成第二间隔物，然后在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。 进行固相外延处理以将掺杂的源极/漏极延伸区域和掺杂的源极/漏极区域转换成源极/漏极端子。 在前非晶化注入中，使用离子半径大于锗离子的掺杂剂。

公开(公告)号：US5611511A

公开(公告)日：1997-03-18

申请号：US572853

申请日：1995-12-14

Applicant: Chun-yi Lee

Inventor： Chun-yi Lee

IPC: F16B47/00 ,  A45D42/14

CPC classification number: F16B47/00

Abstract: A sucker structure includes a disk body having a rim portion, a supporting base formed on an upper portion of the disk body, a flexible snapping member mounted on an upper portion of the supporting base, and a drawing strip having a first end portion attached to the rim portion of the disk body and a second end portion attached to one distal end of the snapping member.

Abstract translation: 吸盘结构包括具有边缘部分的盘体，形成在盘体上部的支撑基座，安装在支撑基座的上部上的柔性卡扣构件以及附接到 盘体的边缘部分和附接到卡扣构件的一个远端的第二端部。

公开(公告)号：US08703594B2

公开(公告)日：2014-04-22

申请号：US13280770

申请日：2011-10-25

Applicant: Ming-Hsi Yeh ,  Tsung-Chieh Tsai ,  Chun-Yi Lee

Inventor： Ming-Hsi Yeh ,  Tsung-Chieh Tsai ,  Chun-Yi Lee

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092

Abstract: A method for fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features in an inter-layer dielectric (ILD) over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. Source/drain (S/D) features are formed at edges of the active gate features in the substrate for forming transistor devices. The disclosed method provides an improved method for reducing parasitic capacitance among the transistor devices. In an embodiment, the improved formation method is achieved by introducing species into the dummy gate feature to increase the resistance of the dummy gate feature.

Abstract translation: 公开了一种制造半导体器件的方法。 在衬底上的层间电介质（ILD）中的两个有源栅极特征之间形成虚拟栅极特征。 隔离结构位于衬底中，虚拟栅极特征位于隔离结构之上。 源极/漏极（S / D）特征形成在用于形成晶体管器件的衬底中的有源栅极特征的边缘处。 所公开的方法提供了一种用于减小晶体管器件之间的寄生电容的改进方法。 在一个实施例中，通过将物质引入虚拟栅极特征来增加虚拟栅极特征的电阻来实现改进的形成方法。