公开(公告)号：US07706189B2

公开(公告)日：2010-04-27

申请号：US11753963

申请日：2007-05-25

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/12

摘要： To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb.

摘要翻译： 为了对一个或多个非易失性存储元件进行编程，例如通过公共字线将一组编程脉冲施加到至少一个选定的非易失性存储元件和一个或多个特定未选择的非易失性存储元件。 在编程过程期间将升压电压施加到其它未选择的非易失性存储元件，以便增强未选择的非易失性存储元件的通道，从而禁止编程。 每个编程脉冲具有第一中间幅度，第二中间幅度和第三幅度。 在一个实施例中，第一中间幅度与升压电压相似或相同。 第二中间幅度大于第一中间幅度，但小于第三幅度。 这样的布置可以减少节目干扰的影响。

公开(公告)号：US07656703B2

公开(公告)日：2010-02-02

申请号：US11753958

申请日：2007-05-25

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/10

摘要： To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb.

摘要翻译： 为了对一个或多个非易失性存储元件进行编程，例如通过公共字线将一组编程脉冲施加到至少一个选定的非易失性存储元件和一个或多个特定未选择的非易失性存储元件。 在编程过程期间将升压电压施加到其它未选择的非易失性存储元件，以便增强未选择的非易失性存储元件的通道，使得编程将被禁止。 每个编程脉冲具有第一中间幅度，第二中间幅度和第三幅度。 在一个实施例中，第一中间幅度与升压电压相似或相同。 第二中间幅度大于第一中间幅度，但小于第三幅度。 这样的布置可以减少节目干扰的影响。

公开(公告)号：US20090080245A1

公开(公告)日：2009-03-26

申请号：US11861135

申请日：2007-09-25

申请人： Jeffrey W. Lutze ,  Dana Lee

发明人： Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C5/02 ,  G11C16/04 ,  H01L21/8247

CPC分类号： H01L27/1158 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11568 ,  H01L27/1157

摘要： A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.

摘要翻译： 公共活动层上的多个非易失性存储元件偏离邻近的非易失性存储元件。 非易失性存储元件的这种抵消有助于减少邻近非易失性存储元件的干扰。 还描述了制造偏移非易失性存储元件的制造方法。

公开(公告)号：US07463531B2

公开(公告)日：2008-12-09

申请号：US11618606

申请日：2006-12-29

申请人： Gerrit Jan Hemink ,  Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Gerrit Jan Hemink ,  Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at different voltages for particular non-volatile storage elements.

摘要翻译： 在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。 在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。 在预充电期间，对于特定的非易失性存储元件，以不同的电压提供一个或多个预充电使能信号。

公开(公告)号：US20080291736A1

公开(公告)日：2008-11-27

申请号：US11753963

申请日：2007-05-25

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/12

摘要： To program one or more non-volatile storage elements, a set of programming pulses are applied to at least one selected non-volatile storage element and one or more particular unselected non-volatile storage elements, for example, via a common word line. A boosting voltage is applied to other unselected non-volatile storage elements during the programming process in order to boost the channels of the unselected non-volatile storage elements so that programming will be inhibited. Each of the programming pulses has a first intermediate magnitude, a second intermediate magnitude and a third magnitude. In one embodiment, the first intermediate magnitude is similar to or the same as the boosting voltage. The second intermediate magnitude is greater than the first intermediate magnitude, but less then the third magnitude. Such an arrangement can reduce the effects of program disturb.

摘要翻译： 为了对一个或多个非易失性存储元件进行编程，例如通过公共字线将一组编程脉冲施加到至少一个选定的非易失性存储元件和一个或多个特定未选择的非易失性存储元件。 在编程过程期间将升压电压施加到其它未选择的非易失性存储元件，以便增强未选择的非易失性存储元件的通道，从而禁止编程。 每个编程脉冲具有第一中间幅度，第二中间幅度和第三幅度。 在一个实施例中，第一中间幅度与升压电压相似或相同。 第二中间幅度大于第一中间幅度，但小于第三幅度。 这样的布置可以减少节目干扰的影响。

公开(公告)号：US07180127B2

公开(公告)日：2007-02-20

申请号：US10872052

申请日：2004-06-17

申请人： Bomy Chen ,  Dana Lee

发明人： Bomy Chen ,  Dana Lee

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7885

摘要： A method of forming a floating gate memory cell array, and the array formed thereby, wherein a trench is formed into the surface of a semiconductor substrate. The source and drain regions are formed underneath the trench and along the substrate surface, respectively, with a non-linear channel region therebetween. The floating gate has a lower portion disposed in the trench and an upper portion disposed above the substrate surface and having a lateral protrusion extending parallel to the substrate surface. The lateral protrusion is formed by etching a cavity into an exposed end of a sacrificial layer and filling it with polysilicon. The control gate is formed about the lateral protrusion and is insulated therefrom. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge that points toward the floating gate and in a direction opposite to that of the lateral protrusion.

摘要翻译： 一种形成浮栅存储单元阵列的方法和由此形成的阵列，其中沟槽形成在半导体衬底的表面中。 源极和漏极区分别形成在沟槽下方并且沿着衬底表面，其间具有非线性沟道区。 浮动栅极具有设置在沟槽中的下部和设置在基板表面上方并具有平行于基板表面延伸的横向突起的上部。 横向突起通过将空腔蚀刻到牺牲层的暴露端并用多晶硅填充而形成。 控制门围绕横向突起形成并与其绝缘。 沟槽侧壁以锐角与衬底表面相接触以形成指向浮动栅极并且沿与横向突起的方向相反的方向的尖锐边缘。

公开(公告)号：US07161844B2

公开(公告)日：2007-01-09

申请号：US10814443

申请日：2004-03-30

申请人： Vishal Sarin ,  Hieu Van Tran ,  Dana Lee

发明人： Vishal Sarin ,  Hieu Van Tran ,  Dana Lee

IPC分类号： G11C7/10

CPC分类号： G11C16/0433 ,  G11C7/12 ,  G11C16/10

摘要： A bitline leakage current compensation circuit for compensating for leakage current in an operational memory array by measuring the leakage current in a non-operational memory array or a dummy memory array and providing a feedback signal to a current source or providing the compensation current.

摘要翻译： 一种位线泄漏电流补偿电路，用于通过测量非操作存储器阵列或虚拟存储器阵列中的漏电流并向电流源提供反馈信号或提供补偿电流来补偿操作存储器阵列中的漏电流。

公开(公告)号：US20060273378A1

公开(公告)日：2006-12-07

申请号：US11134557

申请日：2005-05-20

申请人： Feng Gao ,  Ya-Fen Lin ,  John Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

发明人： Feng Gao ,  Ya-Fen Lin ,  John Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

IPC分类号： H01L29/792

CPC分类号： H01L29/42336 ,  G11C16/0425 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328

摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

摘要翻译： 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，由此在其间限定沟道区域。 多个浮动栅极彼此间隔开并且各自与沟道区域绝缘。 多个控制栅极彼此间隔开，每个控制栅极与沟道区域绝缘。 每个控制栅极位于一对浮动栅极之间，并且电容耦合到该对浮置栅极。 多个选择栅极彼此间隔开，每个选择栅极与沟道区域绝缘。 每个选择门位于一对浮动门之间。

公开(公告)号：US20060261399A1

公开(公告)日：2006-11-23

申请号：US11134540

申请日：2005-05-20

申请人： Yuniarto Widjaja ,  John Cooksey ,  Changyuan Chen ,  Feng Gao ,  Ya-Fen Lin ,  Dana Lee

发明人： Yuniarto Widjaja ,  John Cooksey ,  Changyuan Chen ,  Feng Gao ,  Ya-Fen Lin ,  Dana Lee

IPC分类号： H01L29/788

CPC分类号： G11C16/0425 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3431 ,  G11C2216/18 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.

摘要翻译： 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括在衬底中具有第二导电类型的第二区域的第二导电类型的第一区域，与第一区域间隔开。 在第一区域和第二区域之间限定连续的第一通道区域。 多个浮动栅极彼此间隔开，每个浮置栅极位于沟道区域的独立部分上。 设置有多个控制栅极，每个与浮动栅极相关联并与其相邻。 每个控制栅极具有两个部分：沟道区域的一部分上的第一部分和相关联的浮动栅极上的第二部分，并与其电容耦合。

公开(公告)号：US06992909B2

公开(公告)日：2006-01-31

申请号：US11157318

申请日：2005-06-20

申请人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

发明人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

IPC分类号： G11C17/00

CPC分类号： H01L27/112 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/1126 ,  H01L27/11266

摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

摘要翻译： 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 门间隔开并与通道的至少第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。