中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

80 records (took 0.017 seconds)

    USER INTERFACE APPARATUS AND METHOD USING MOVEMENT RECOGNITION
    52.
    发明申请
    USER INTERFACE APPARATUS AND METHOD USING MOVEMENT RECOGNITION 有权
    用户界面装置和使用运动识别的方法

    公开(公告)号：US20120106792A1

    公开(公告)日：2012-05-03

    申请号：US13285314

    申请日：2011-10-31

    Applicant: Woo-Sung KANG ,  Mu-Sik Kwon ,  Jung-Rim Kim ,  Seong-Taek Hwang ,  Dong-Hyuk Lee

    Inventor： Woo-Sung KANG ,  Mu-Sik Kwon ,  Jung-Rim Kim ,  Seong-Taek Hwang ,  Dong-Hyuk Lee

    IPC: G06K9/00

    CPC classification number: G06K9/00355 ,  G06F3/017 ,  G06K9/00228

    Abstract: A movement recognition method and a user interface are provided. A skin color is detected from a reference face area of an image. A movement-accumulated area, in which movements are accumulated, is detected from sequentially accumulated image frames. Movement information corresponding to the skin color is detected from the detected movement-accumulated area. A user interface screen is created and displayed using the detected movement information.

    Abstract translation: 提供了运动识别方法和用户界面。 从图像的参考面区域检测肤色。 从顺序累积的图像帧检测运动累积区域，其中运动被累积。 从检测到的移动累积区域检测与肤色对应的运动信息。 使用检测到的移动信息创建和显示用户界面屏幕。

    Multipath accessible semiconductor memory device with host interface between processors
    54.
    发明授权
    Multipath accessible semiconductor memory device with host interface between processors 有权
    多路径可访问的半导体存储器件，具有处理器之间的主机接口

    公开(公告)号：US07941612B2

    公开(公告)日：2011-05-10

    申请号：US11829859

    申请日：2007-07-27

    Applicant: Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Dong-Hyuk Lee ,  Jong-Wook Park ,  Ho-Cheol Lee ,  Mi-Jo Kim ,  Jung-Sik Kim ,  Chang-Ho Lee

    Inventor： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Dong-Hyuk Lee ,  Jong-Wook Park ,  Ho-Cheol Lee ,  Mi-Jo Kim ,  Jung-Sik Kim ,  Chang-Ho Lee

    IPC: G06F12/00

    CPC classification number: G11C7/1075 ,  G11C7/1012 ,  G11C11/4096

    Abstract: A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

    Abstract translation: 多路可及半导体存储器件提供处理器之间的接口功能。 存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径 响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

    Semiconductor memory device having connected bit lines and data shift method thereof
    55.
    发明授权
    Semiconductor memory device having connected bit lines and data shift method thereof 有权
    具有连接位线的半导体存储器件及其数据移位方法

    公开(公告)号：US07457188B2

    公开(公告)日：2008-11-25

    申请号：US11457050

    申请日：2006-07-12

    Applicant: Dong-Hyuk Lee

    Inventor： Dong-Hyuk Lee

    IPC: G11C8/00

    CPC classification number: G11C7/18 ,  G11C7/1006 ,  G11C7/12 ,  G11C2207/002

    Abstract: Provided is a semiconductor memory device having connected bit lines and a data shifting method thereof. An embodiment of the semiconductor memory device includes a plurality of memory cell blocks each including a plurality of bit lines and a plurality of word lines, a plurality of sense amplifier blocks respectively disposed between the memory cell blocks, wherein each sense amplifier block includes a plurality of sense amplifier circuits corresponding to the bit lines, and a plurality of switches. The switches connect bit lines not sharing a sense amplifier block among bit lines of adjacent memory cell blocks between which the sense amplifier block is disposed, in response to a shift signal. Therefore, in the semiconductor memory device and the data shift method thereof, it is possible to easily shift data stored in memory cells connected to an arbitrary word line to memory cells connected to another arbitrary word line.

    Abstract translation: 提供了具有连接的位线及其数据移位方法的半导体存储器件。 半导体存储器件的实施例包括多个存储单元块，每个存储单元块包括多个位线和多个字线，分别设置在存储单元块之间的多个读出放大器块，其中每个读出放大器块包括多个 对应于位线的读出放大器电路，以及多个开关。 这些开关响应于移位信号，连接在相邻的存储单元块的位线之间不共享读出放大器块的位线，其间设置有读出放大器块。 因此，在半导体存储器件及其数据移位方法中，可以容易地将连接到任意字线的存储单元中存储的数据移位到连接到另一任意字线的存储单元。

    Row address code selection based on locations of substandard memory cells
    60.
    发明授权
    Row address code selection based on locations of substandard memory cells 有权
    基于不合格存储单元位置的行地址码选择

    公开(公告)号：US08520461B2

    公开(公告)日：2013-08-27

    申请号：US12832208

    申请日：2010-07-08

    Applicant: Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

    Inventor： Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

    IPC: G11C7/00

    CPC classification number: G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C17/16 ,  G11C2211/4061

    Abstract: A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to ensure that memory blocks having substandard memory cells, which must be refreshed more frequently than other cells, are refreshed together, while memory blocks without substandard memory cells are refreshed together.

    Abstract translation: 存储器设备识别包含不合标准存储器单元的存储器块。 然后，存储器件在刷新操作期间确定应用于存储器块的行地址代码。 行地址代码确定存储器块的哪些存储器块被一起刷新。 行地址码被设计为确保具有不同于其它单元的频率更新的不合格存储器单元的存储器块被一起刷新，而没有不合格存储器单元的存储器块被刷新在一起。

Patent Agency Ranking