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    Internal power generating apparatus, multichannel memory including the same, and processing system employing the multichannel memory
    3.
    发明授权
    Internal power generating apparatus, multichannel memory including the same, and processing system employing the multichannel memory 有权
    内部发电装置，包括该内部发电装置的多通道存储器，以及采用多通道存储器的处理系统

    公开(公告)号：US08315121B2

    公开(公告)日：2012-11-20

    申请号：US12900624

    申请日：2010-10-08

    申请人： Jung-sik Kim ,  Ho-cheol Lee ,  Jang-woo Ryu

    发明人： Jung-sik Kim ,  Ho-cheol Lee ,  Jang-woo Ryu

    IPC分类号： G11C5/14

    CPC分类号： G06F1/26 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

    摘要： An internal power generating system for a semiconductor device is disclosed. The device may include a plurality of channels. The system comprises a reference voltage generator configured to generate a reference voltage. The system further comprises a plurality of internal power generators that are allocated to the plurality of channels in one-to-one correspondence and that are configured to commonly use the reference voltage generated by the reference voltage generator. Each internal power generator may be configured to receive a fed back internal power voltage, to compare the fed back internal power voltage to the reference voltage, and to generate an internal power voltage based on the comparison. The system further comprises a plurality of channel state detectors that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively detect operation states of the plurality of channels based on separate respective sets of command signals for each channel. The system additional comprises a plurality of internal power controllers that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively control driving capabilities for the internal power voltages according to the detected operation states.

    摘要翻译： 公开了一种用于半导体器件的内部发电系统。 该设备可以包括多个信道。 该系统包括被配置为产生参考电压的参考电压发生器。 该系统还包括多个内部功率发生器，其以一一对应的方式分配给多个通道，并且被配置为共同使用由参考电压发生器产生的参考电压。 每个内部发电机可以被配置为接收反馈内部电力电压，以将反馈内部电力电压与参考电压进行比较，并且基于该比较来产生内部电力电压。 该系统还包括多个通道状态检测器，其以一一对应的方式分配给多个通道，并且被配置为分别基于各个命令信号分别检测多个通道的操作状态 渠道。 该系统附加包括一对一对应地分配给多个通道的多个内部功率控制器，并且被配置为分别根据检测到的操作状态来控制内部电源电压的驱动能力。

    INTERNAL POWER GENERATING APPARATUS, MULTICHANNEL MEMORY INCLUDING THE SAME, AND PROCESSING SYSTEM EMPLOYING THE MULTICHANNEL MEMORY
    4.
    发明申请
    INTERNAL POWER GENERATING APPARATUS, MULTICHANNEL MEMORY INCLUDING THE SAME, AND PROCESSING SYSTEM EMPLOYING THE MULTICHANNEL MEMORY 有权
    内部发电装置，包括其的多通道存储器和使用多通道存储器的处理系统

    公开(公告)号：US20110090754A1

    公开(公告)日：2011-04-21

    申请号：US12900624

    申请日：2010-10-08

    申请人： Jung-sik Kim ,  Ho-cheol Lee ,  Jang-woo Ryu

    发明人： Jung-sik Kim ,  Ho-cheol Lee ,  Jang-woo Ryu

    IPC分类号： G11C5/14 ,  G05F1/10

    CPC分类号： G06F1/26 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

    摘要： An internal power generating system for a semiconductor device is disclosed. The device may include a plurality of channels. The system comprises a reference voltage generator configured to generate a reference voltage. The system further comprises a plurality of internal power generators that are allocated to the plurality of channels in one-to-one correspondence and that are configured to commonly use the reference voltage generated by the reference voltage generator. Each internal power generator may be configured to receive a fed back internal power voltage, to compare the fed back internal power voltage to the reference voltage, and to generate an internal power voltage based on the comparison. The system further comprises a plurality of channel state detectors that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively detect operation states of the plurality of channels based on separate respective sets of command signals for each channel. The system additional comprises a plurality of internal power controllers that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively control driving capabilities for the internal power voltages according to the detected operation states.

    摘要翻译： 公开了一种用于半导体器件的内部发电系统。 该设备可以包括多个信道。 该系统包括被配置为产生参考电压的参考电压发生器。 该系统还包括多个内部功率发生器，其以一一对应的方式分配给多个通道，并且被配置为共同使用由参考电压发生器产生的参考电压。 每个内部发电机可以被配置为接收反馈内部电力电压，以将反馈内部电力电压与参考电压进行比较，并且基于该比较来产生内部电力电压。 该系统还包括多个通道状态检测器，其以一一对应的方式分配给多个通道，并且被配置为分别基于各个命令信号分别检测多个通道的操作状态 渠道。 该系统附加包括一对一对应地分配给多个通道的多个内部功率控制器，并且被配置为分别根据检测到的操作状态来控制内部电源电压的驱动能力。

    Synchronous dynamic random access memory semiconductor device for controlling output data
    6.
    发明授权
    Synchronous dynamic random access memory semiconductor device for controlling output data 有权
    用于控制输出数据的同步动态随机存取存储器半导体器件

    公开(公告)号：US08325544B2

    公开(公告)日：2012-12-04

    申请号：US12702809

    申请日：2010-02-09

    申请人： Sang-kyu Kang ,  Ho-cheol Lee ,  Chi-sung Oh

    发明人： Sang-kyu Kang ,  Ho-cheol Lee ,  Chi-sung Oh

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response to an externally input signal. The strobe buffers are connected to the output buffers and the strobe control unit, and each of the strobe buffers is configured to output at least one strobe signal. At least some of the strobe buffers are activated in response to the strobe control signals, and the output buffers are activated in response to the strobe signals output by the activated strobe buffers.

    摘要翻译： 提供了包括多个输出缓冲器，选通控制单元和多个选通缓冲器的同步动态随机存取存储器（DRAM）半导体器件。 每个输出缓冲器都配置为输出一位数据。 选通控制单元被配置为响应于外部输入信号输出多个选通控制信号。 选通缓冲器连接到输出缓冲器和选通控制单元，并且每个选通缓冲器被配置为输出至少一个选通信号。 至少一些选通缓冲器响应于选通控制信号被激活，并且输出缓冲器响应于被激活的选通缓冲器输出的选通信号被激活。

    Redundancy fuse box and method for arranging the same
    8.
    发明授权
    Redundancy fuse box and method for arranging the same 失效
    冗余保险丝盒及其布置方法

    公开(公告)号：US6067268A

    公开(公告)日：2000-05-23

    申请号：US110630

    申请日：1998-07-06

    申请人： Ho-cheol Lee

    发明人： Ho-cheol Lee

    IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C11/41 ,  G11C29/00 ,  G11C29/04 ,  H01L27/10 ,  G11C7/00

    CPC分类号： G11C29/80 ,  G11C29/781 ,  G11C29/785

    摘要： A redundancy fuse box of a semiconductor memory device which minimizes address line loading by organizing fuse cells into fuse cell groups sharing the same sub-address line. The address signal therefore has to traverse across a shorter distance along the semiconductor device, which contributes to a reduction in cell line loading. The redundancy fuse box includes a plurality of fuse cells, each having a transistor and fuse, to which an address signal of a memory cell is applied. The respective fuse boxes are constructed as one fuse box by being laid out in the same place. The fuse box includes a plurality of fuse cells which receive the same address signal along a common sub-address line and is wired so that outputs of the fuse cells which received the same address signal contribute to different redundancy enable signals.

    摘要翻译： 一种半导体存储器件的冗余保险丝盒，其通过将熔丝单元组织成共享相同子地址线的熔丝单元组来最小化地址线负载。 因此，地址信号必须穿过半导体器件的较短距离，这有助于细胞系负载的减少。 冗余保险丝盒包括多个熔丝单元，每个熔丝单元具有晶体管和熔丝，施加存储单元的地址信号。 各保险丝盒通过布置在同一个地方构成一个保险丝盒。 保险丝盒包括多个熔丝单元，其沿公共子地址线接收相同的地址信号，并被布线，使得接收相同地址信号的熔丝单元的输出有助于不同的冗余使能信号。

    Layout arrangements of fuse boxes for integrated circuit devices, including bent and straight fuses
    9.
    发明授权
    Layout arrangements of fuse boxes for integrated circuit devices, including bent and straight fuses 有权
    用于集成电路设备的保险丝盒的布局布置，包括弯曲和直接保险丝

    公开(公告)号：US06172896B2

    公开(公告)日：2001-01-09

    申请号：US09351729

    申请日：1999-07-12

    申请人： Ho-cheol Lee

    发明人： Ho-cheol Lee

    IPC分类号： G11C1700

    CPC分类号： G11C17/16

    摘要： An integrated circuit device such as an integrated circuit memory device, includes a first fuse group such as a first laser fuse group including a plurality of first laser fuses each having a first narrow end, a second opposite end which is wider and a bent central portion. Pitches of the first end of the plurality of first laser fuses are narrow and pitches of the second end are wide. The plurality of first laser fuses are adjacent one another. A second fuse group such as a second laser fuse group includes a plurality of second laser fuses each having a first wide end, a second opposite end which is narrower, and a bent central portion. Pitches of the first end of the plurality of second laser fuses are wide and pitches of the second end are narrow. The second plurality of laser fuses are adjacent one another. The first ends of the laser fuses in the first laser fuse group are adjacent the first ends of laser fuses in the second laser fuse group. The second ends of the laser fuses in the first laser fuse group are adjacent the second ends of the laser fuses in the second laser fuse group. The central portions of the outer laser fuses of the first and second laser fuse groups are not bent, but straight. Accordingly, when a specific laser fuse is blown, neighboring laser fuses need not be damaged, and the density of the laser fuse area may be increased.

    摘要翻译： 诸如集成电路存储器件的集成电路器件包括第一熔丝组，例如第一激光熔丝组，其包括多个第一激光熔丝，每个第一激光熔丝具有第一窄端，第二相对端较宽，弯曲的中心部 。 多个第一激光熔丝的第一端的间距窄，第二端的间距较宽。 多个第一激光熔丝彼此相邻。 诸如第二激光熔丝组的第二熔丝组包括多个第二激光熔丝，每个第二激光熔丝具有第一宽端，第二相对端较窄，以及弯曲的中心部。 多个第二激光熔丝的第一端的间距宽，第二端的间距窄。 第二组激光熔丝彼此相邻。 第一激光熔丝组中的激光熔丝的第一端与第二激光熔丝组中的激光熔丝的第一端相邻。 第一激光熔丝组中的激光熔丝的第二端与第二激光熔丝组中的激光熔丝的第二端相邻。 第一和第二激光熔丝组的外部激光熔丝的中心部分不弯曲，而是直的。 因此，当特定的激光熔丝被熔断时，不需要损坏相邻的激光熔丝，并且可以增加激光熔丝区域的密度。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5808948A

    公开(公告)日：1998-09-15

    申请号：US769615

    申请日：1996-12-18

    申请人： Chul-soo Kim ,  Ho-cheol Lee

    发明人： Chul-soo Kim ,  Ho-cheol Lee

    IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/24 ,  G11C7/00

    CPC分类号： G11C29/24

    摘要： There is provided a semiconductor memory device which does not require an additional input pad to apply a signal for discriminating between a normal cell and a redundant cell. The semicodnuctor memory device has (claim 1). Therefore, the normal cell array or the redundant cell array is sequentially selected and tested by using the same input pad to which the bank select bit is input, without an additional pad.

    摘要翻译： 提供了半导体存储器件，其不需要额外的输入焊盘来施加用于区分正常单元和冗余单元的信号。 半导体存储器件具有（权利要求1）。 因此，通过使用输入存储体选择位的相同的输入焊盘，而没有附加的焊盘，顺序地选择和测试正常单元阵列或冗余单元阵列。