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公开(公告)号：US08536675B2
公开(公告)日：2013-09-17
申请号：US13364153
申请日：2012-02-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。
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52.发明授权Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process 失效用于形成PCRAM和自对准回蚀工艺的自对准位线的方法公开(公告)号：US08445313B2
公开(公告)日：2013-05-21
申请号：US13546684
申请日：2012-07-11
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。
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53.发明授权公开(公告)号：US08431486B2
公开(公告)日：2013-04-30
申请号：US12853537
申请日：2010-08-10
申请人： Cyril Cabral, Jr. , Sebastian U. Engelmann , Benjamin Fletcher , Eric A. Joseph , Satyanarayana V. Nitta
发明人： Cyril Cabral, Jr. , Sebastian U. Engelmann , Benjamin Fletcher , Eric A. Joseph , Satyanarayana V. Nitta
IPC分类号： H01L21/44
CPC分类号： H01L21/76816 , H01L21/31116 , H01L21/32136 , H01L21/32139 , H01L21/76804 , H01L21/76877 , H01L21/76885 , H01L23/5283 , H01L23/53214 , H01L23/53228 , H01L23/53242 , H01L23/53257 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.
摘要翻译： 本公开提供了形成到电气设备的互连的方法。 在一个实施例中，形成互连的方法包括在衬底上提供器件层，其中所述器件层包括至少一个电器件，在所述至少一个电器件上的入口电介质，以及与所述至少一个电器件电连接的触点 所述至少一个电气设备。 在器件层上形成互连金属层，并且在互连金属层的一部分上形成含钽蚀刻掩模。 蚀刻互连金属层以提供与至少一个电气设备连通的梯形互连。 梯形互连具有与器件层接触的第一表面，其具有比与含钽蚀刻掩模接触的梯形互连的第二表面更大的宽度。
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公开(公告)号：US08338225B2
公开(公告)日：2012-12-25
申请号：US13350817
申请日：2012-01-16
IPC分类号： H01L21/06
CPC分类号： H01L45/144 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/1683
摘要： A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.
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公开(公告)号：US20120280197A1
公开(公告)日：2012-11-08
申请号：US13550091
申请日：2012-07-16
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译： 一种具有平底下电极的相变存储单元及其制造方法。 该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面 导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极 。
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56.发明申请METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS 有权用于形成用于PCRAM和自对准回退过程的自对准位线的方法公开(公告)号：US20120202333A1
公开(公告)日：2012-08-09
申请号：US13020051
申请日：2011-02-03
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/02
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and fowling at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译： 一种形成与相变材料对准的位线的方法，其包括在下电极的一部分上形成牺牲材料的基座并且与邻近所述牺牲材料的至少一个电介质材料相连，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。
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公开(公告)号：US20120108024A1
公开(公告)日：2012-05-03
申请号：US13345252
申请日：2012-01-06
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L51/001 , B82Y10/00 , H01L51/0048 , H01L51/0541 , H01L51/0558
摘要： A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.
摘要翻译： 场效应晶体管（FET）包括由第一材料形成的漏极，由第一材料形成的源极，由将源极耦合到漏极的纳米结构形成的沟道以及在源极和漏极之间形成的栅极， 纳米结构。
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58.发明授权公开(公告)号：US08138056B2
公开(公告)日：2012-03-20
申请号：US12497596
申请日：2009-07-03
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。
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公开(公告)号：US08101456B2
公开(公告)日：2012-01-24
申请号：US12243759
申请日：2008-10-01
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/1683
摘要： A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.
摘要翻译： 存储单元结构和形成这种结构的方法。 该方法部分地包括在底部电极的中心上形成氧化层内的通孔。 该方法包括沿通孔的侧壁沉积通孔间隔物并氧化通孔间隔物。 通孔间隔件由具有至少一个半的起珠床比的材料组成，并且当被氧化时是绝缘体。 在氧化期间通孔间隔物的膨胀减小了通孔面积。 或者，该方法部分地包括在底部电极的中心之上在第一层内形成通孔。 第一层具有至少一个半的Pilling-Bedworth比，并且当被氧化时是绝缘体。 该方法还包括在第一层中氧化通孔的侧壁的至少一部分。
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公开(公告)号：US20120008362A1
公开(公告)日：2012-01-12
申请号：US12833446
申请日：2010-07-09
CPC分类号： G11C19/0808 , G11C11/14 , G11C11/161 , G11C11/1675
摘要： A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material.
摘要翻译： 一种用于形成存储器件的方法包括：形成具有在衬底中具有波状轮廓的内表面的空腔，在所述空腔中沉积铁磁材料，在所述衬底上形成接近所述铁磁材料的一部分的读取元件，以及形成 在基板上的写入元件靠近铁磁材料的第二部分。
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