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    Implementing decoupling capacitors with hot-spot thermal reduction on integrated circuit chips
    51.
    发明授权
    Implementing decoupling capacitors with hot-spot thermal reduction on integrated circuit chips 失效
    在集成电路芯片上实现热点热还原的去耦电容

    公开(公告)号：US07723816B2

    公开(公告)日：2010-05-25

    申请号：US12186837

    申请日：2008-08-06

    申请人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    发明人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    IPC分类号： H01L27/01 ,  H01L31/058

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0805

    摘要： A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.

    摘要翻译： 提供了一种方法和结构，用于在包括绝缘体上硅（SOI）电路的集成电路芯片上实现具有热点热还原的去耦电容器。 绝缘体上硅（SOI）结构包括硅衬底层，由硅衬底层承载的薄掩埋氧化物（BOX）层以及由薄BOX层承载的有源层。 在有源层中的热点区域附近建立导热路径，以减少热效应，包括来自SOI结构背面的背面热连接。 背面热连接包括从SOI结构的背面延伸到硅衬底层中的背面蚀刻开口，形成在所述背面蚀刻开口上的电容器电介质; 以及沉积在填充所述背面蚀刻开口的所述电容器电介质上的热连接材料。

    Implementing Reduced Hot-Spot Thermal Effects for SOI Circuits
    52.
    发明申请
    Implementing Reduced Hot-Spot Thermal Effects for SOI Circuits 审中-公开
    实现SOI电路降低热点热效应

    公开(公告)号：US20100019385A1

    公开(公告)日：2010-01-28

    申请号：US12178029

    申请日：2008-07-23

    申请人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    发明人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    IPC分类号： H01L21/71 ,  H01L23/34

    CPC分类号： H01L23/3677 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods and structures are provided for implementing reduced hot spot thermal effects for silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, an active layer carried by the thin BOX layer, and a pad oxide layer carried by the active layer. A thermal conductive path is built to reduce thermal effects of a hotspot area in the active layer and extends from the active layer to the backside of the SOI structure. A trench etched from the topside to the active layer, and is filled with a thermal connection material. A thermal connection from a backside of the SOI structure includes an opening etched into the silicon substrate layer from the backside and filled with a thermal connection material.

    摘要翻译： 提供了用于实现绝缘体上硅（SOI）电路的减少热点热效应的方法和结构。 绝缘体上硅（SOI）结构包括硅衬底层，由硅衬底层承载的薄掩埋氧化物（BOX）层，由薄BOX层承载的有源层和由活性层承​​载的衬垫氧化物层 层。 建立导热路径以减少有源层中的热点区域的热效应并且从有源层延伸到SOI结构的背面。 从顶部蚀刻到有源层的沟槽，并填充有热连接材料。 来自SOI结构的背面的热连接包括从背面蚀刻到硅衬底层中并且填充有热连接材料的开口。

    Memory controller for daisy chained memory chips
    53.
    发明授权
    Memory controller for daisy chained memory chips 失效
    内存控制器，用于菊花链式存储芯片

    公开(公告)号：US07627711B2

    公开(公告)日：2009-12-01

    申请号：US11459966

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G06F12/06

    CPC分类号： G06F13/4243 ,  G06F13/4256

    摘要： A memory controller configured to control a daisy chain of memory chips. The memory controller receives read and write requests from a processor, determines a daisy chain of memory chips that the request is directed to, determines which memory chip in the chain of memory chips the request is directed to, and transmits an address/command word recognizable by the correct memory chip. The memory controller sends write data words to the daisy chain of memory chips that can be associated by the correct memory chip for writing into the correct memory chip. The memory controller receives read data words from the daisy chain of memory chips and returns the read data to the processor. The memory controller transmits a bus clock to the daisy chain of memory chips for controlling transmission of address/command words and data words.

    摘要翻译： 存储器控制器，被配置为控制存储器芯片的菊花链。 存储器控制器从处理器接收读取和写入请求，确定请求所针对的存储器芯片的菊花链，确定请求所针对的存储器芯片链中的哪个存储器芯片，并发送可识别的地址/命令字 由正确的内存芯片。 存储器控制器将写数据字发送到存储器芯片的菊花链，其可由正确的存储器芯片关联以写入正确的存储器芯片。 存储器控制器从存储器芯片的菊花链接收读取的数据字，并将读取的数据返回给处理器。 存储器控制器将总线时钟发送到存储器芯片的菊花链，用于控制地址/命令字和数据字的传输。

    Memory Controller for Daisy Chained Self Timed Memory Chips
    59.
    发明申请
    Memory Controller for Daisy Chained Self Timed Memory Chips 失效
    用于菊花链自定时存储器芯片的存储控制器

    公开(公告)号：US20080028177A1

    公开(公告)日：2008-01-31

    申请号：US11459961

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G06F13/00

    CPC分类号： G06F13/1668

    摘要： A memory controller for controlling a daisy chain of self timed memory chips. The memory controller has information as to how long each self timed memory chip in the daisy chain of memory chips takes to make a read access and a write access to an array on the self timed memory chip. The memory controller determines current access time information on a memory chip by sending a command to the memory chip. The memory chip returns a data word containing the current access time information. Alternatively, the memory controller transmits an address/command word to the memory chip and, after completing an access, transmits a responsive data word to the memory controller. The memory controller determines the access time information using the interval from transmission of the address/command word to reception of the responsive data word.

    摘要翻译： 用于控制自定时存储器芯片的菊花链的存储器控​​制器。 存储器控制器具有关于存储器芯片的菊花链中的每个自定时存储器芯片对自定时存储器芯片进行读取访问和写入访问多长时间的信息的信息。 存储器控制器通过向存储器芯片发送命令来确定存储器芯片上的当前访问时间信息。 存储器芯片返回包含当前访问时间信息的数据字。 或者，存储器控制器将地址/命令字发送到存储器芯片，并且在完成访问之后，将响应数据字发送到存储器控制器。 存储器控制器使用从地址/命令字的发送到响应数据字的接收的间隔来确定访问时间信息。

    CARRIER HAVING DAISY CHAIN OF SELF TIMED MEMORY CHIPS
    60.
    发明申请
    CARRIER HAVING DAISY CHAIN OF SELF TIMED MEMORY CHIPS 失效
    具有自定义记忆卡的DAISY链的承运人

    公开(公告)号：US20080028160A1

    公开(公告)日：2008-01-31

    申请号：US11459983

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G06F13/00 ,  G06F12/00

    CPC分类号： G06F13/1684 ,  G11C7/10

    摘要： A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to an address/command bus off-carrier connector. An array on a memory chip has an access time dynamically determined by how fast the array can be accessed.

    摘要翻译： 一种在存储器芯片的菊花链中具有至少一个自定时存储器芯片的载体。 第一载体具有连接到第一载体的存储芯片的菊链的至少一部分。 第一载波上的地址/命令总线输入将地址/命令字携带到存储器芯片的菊花链中的第一存储器芯片。 如果第一存储器芯片确定地址/命令字不指向第一存储器芯片，则第一存储器芯片使用点对点将地址/命令字重新驱动到存储器芯片的菊花链中的第二存储器芯片 地址/命令总线链路。 如果第一个载波上没有更多的存储器芯片，则地址/命令字被重新驱动到地址/命令总线非承载连接器。 存储器芯片上的阵列具有动态确定阵列可访问速度的访问时间。