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    Method, Apparatus, and System for Manageability and Secure Routing and Endpoint Access
    1.
    发明申请
    Method, Apparatus, and System for Manageability and Secure Routing and Endpoint Access 有权
    用于可管理性和安全路由和端点访问的方法，设备和系统

    公开(公告)号：US20150096051A1

    公开(公告)日：2015-04-02

    申请号：US14565833

    申请日：2014-12-10

    申请人： Mahesh NATU ,  Eric DAHLEN

    发明人： Mahesh NATU ,  Eric DAHLEN

    IPC分类号： G06F21/85

    CPC分类号： G06F21/85 ,  G06F13/4027 ,  G06F2221/2141 ,  H04L63/101 ,  H04L63/104 ,  H04L63/20

    摘要： A solution is presented to securing endpoints without the need for a separate bus or communication path. The solution allows for controlling access to endpoints by utilizing a management protocol by overlapping with existing interconnect communication paths in a packet format and utilizing a PCI address BDF (Bus number, Device number, and Function number) for verification.

    摘要翻译： 提供了解决方案来保护端点，而不需要单独的总线或通信路径。 该解决方案允许通过利用管理协议控制对端点的访问，通过与分组格式的现有互连通信路径重叠并利用PCI地址BDF（总线号码，设备号码和功能号码）进行验证。

    Enabling idle states for a component associated with an interconnect
    2.
    发明授权
    Enabling idle states for a component associated with an interconnect 有权
    启用与互连关联的组件的空闲状态

    公开(公告)号：US07734942B2

    公开(公告)日：2010-06-08

    申请号：US11646932

    申请日：2006-12-28

    申请人： Eric Dahlen ,  Jimbo Alexander ,  Parthipan Satchi

    发明人： Eric Dahlen ,  Jimbo Alexander ,  Parthipan Satchi

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3203

    摘要： In one embodiment, the present invention includes a method for receiving an information packet in a first port from an interconnect while an agent associated with the first port is in an idle low power state, transmitting a first signal from the first port along the interconnect to request re-transmission of the information packet, and sending a second signal from the first port to the agent to cause the agent to enter a fully active power state. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括一种用于在与第一端口相关联的代理处于空闲低功率状态的同时从互连接收第一端口中的信息分组的方法，沿着互连将第一信号从第一端口传输到 请求信息包的重新发送，以及从第一端口向代理发送第二信号以使代理进入完全有效的电力状态。 描述和要求保护其他实施例。

    Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction on Integrated Circuit Chips
    3.
    发明申请
    Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction on Integrated Circuit Chips 失效
    在集成电路芯片上实现热点热还原实现去耦电容

    公开(公告)号：US20100032799A1

    公开(公告)日：2010-02-11

    申请号：US12186837

    申请日：2008-08-06

    申请人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    发明人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0805

    摘要： A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.

    摘要翻译： 提供了一种方法和结构，用于在包括绝缘体上硅（SOI）电路的集成电路芯片上实现具有热点热还原的去耦电容器。 绝缘体上硅（SOI）结构包括硅衬底层，由硅衬底层承载的薄掩埋氧化物（BOX）层以及由薄BOX层承载的有源层。 在有源层中的热点区域附近建立导热路径，以减少热效应，包括来自SOI结构背面的背面热连接。 背面热连接包括从SOI结构的背面延伸到硅衬底层的后侧蚀刻开口，形成在所述背面蚀刻开口上的电容器电介质; 以及沉积在填充所述背面蚀刻开口的所述电容器电介质上的热连接材料。

    Daisy chainable memory chip
    4.
    发明授权
    Daisy chainable memory chip 失效
    菊花链式存储芯片

    公开(公告)号：US07480201B2

    公开(公告)日：2009-01-20

    申请号：US11872108

    申请日：2007-10-15

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G11C8/00 ,  G11C5/06 ,  G11C5/00

    CPC分类号： G11C29/26 ,  G06F13/4243 ,  G11C5/04 ,  G11C8/12 ,  G11C29/32 ,  G11C2029/3202

    摘要： A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip. If not, the memory chip re-drives the address/command word on a first output. Write data is received as part of the address/command word or from a first data bus port. A bus clock is received and is used to receive and transmit information on the first input, the first output, the first data bus port and the second data bus port. The memory chip is incorporated into a design structure that is embodied in a computer readable medium used for designing, manufacturing, or testing the memory chip.

    摘要翻译： 适用于存储芯片的菊花链的存储芯片。 存储器芯片在第一输入端接收地址/命令字，确定地址命令字是否被引导到存储器芯片; 如果是这样，则存储器芯片访问存储器芯片上的阵列。 如果不是，则存储器芯片在第一输出上重新驱动地址/命令字。 作为地址/命令字的一部分或从第一数据总线端口接收写入数据。 接收总线时钟并用于接收和发送关于第一输入，第一输出，第一数据总线端口和第二数据总线端口的信息。 存储器芯片被并入设计结构中，其体现在用于设计，制造或测试存储器芯片的计算机可读介质中。

    Method and Apparatus for Implementing Redundant Memory Access Using Multiple Controllers on the Same Bank of Memory
    5.
    发明申请
    Method and Apparatus for Implementing Redundant Memory Access Using Multiple Controllers on the Same Bank of Memory 有权
    用于在同一存储器上使用多个控制器实现冗余存储器访问的方法和装置

    公开(公告)号：US20080307253A1

    公开(公告)日：2008-12-11

    申请号：US11872191

    申请日：2007-10-15

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  John Michael Borkenhagen ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  William Paul Hovis

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  John Michael Borkenhagen ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  William Paul Hovis

    IPC分类号： G06F11/16

    CPC分类号： G06F11/2017 ,  G06F2201/85 ,  G11C29/70

    摘要： A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory, and a design structure on which the subject circuit resides is provided. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.

    摘要翻译： 一种方法和装置利用在同一组存储器上的多个控制器实现冗余存储器访问，并且提供了一个主题电路驻留的设计结构。 第一个存储器控制器使用存储器作为其主地址空间，用于存储和提取。 第二个冗余控制器也连接到同一个存储器。 系统控制逻辑用于通知冗余控制器需要接管存储器接口。 如果需要，冗余控制器将初始化并控制存储器。 如果系统必须在冗余模式下被关闭并重新启动，才需要初始化内存。 本发明允许系统在存储器控制器或链路故障期间继续保持并继续运行。

    MEMORY SYSTEM HAVING SELF TIMED DAISY CHAINED MEMORY CHIPS
    10.
    发明申请
    MEMORY SYSTEM HAVING SELF TIMED DAISY CHAINED MEMORY CHIPS 失效
    具有自定义DAISY链接记忆卡的记忆系统

    公开(公告)号：US20080028176A1

    公开(公告)日：2008-01-31

    申请号：US11459957

    申请日：2006-07-26

    申请人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    发明人： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4239

    摘要： A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on a memory chip is determined by a self time block on the memory chip.

    摘要翻译： 一种具有存储器控制器和存储器的存储器系统。 存储器包括一个或多个自定时存储器芯片的菊花链。 地址/命令字通过存储器芯片的菊花链链接并由存储器芯片的菊花链中的一个存储器芯片来处理。 作为地址/命令字的一部分发送要写入存储器芯片的数据，或者在输出数据总线链上传送。 从存储芯片读取的数据在传入数据总线链上传输。 存储器芯片上的访问定时由存储器芯片上的自身时间块确定。