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    Video concept classification using audio-visual atoms
    51.
    发明授权
    Video concept classification using audio-visual atoms 有权
    使用视听原子的视频概念分类

    公开(公告)号：US08135221B2

    公开(公告)日：2012-03-13

    申请号：US12574716

    申请日：2009-10-07

    Applicant: Wei Jiang ,  Courtenay Cotton ,  Shih-Fu Chang ,  Daniel P. Ellis ,  Alexander C. Loui

    Inventor： Wei Jiang ,  Courtenay Cotton ,  Shih-Fu Chang ,  Daniel P. Ellis ,  Alexander C. Loui

    IPC: G06K9/62 ,  G06K9/54

    CPC classification number: G06K9/00765 ,  G10L25/00

    Abstract: A method for determining a classification for a video segment, comprising the steps of: breaking the video segment into a plurality of short-term video slices, each including a plurality of video frames and an audio signal; analyzing the video frames for each short-term video slice to form a plurality of region tracks; analyzing each region track to form a visual feature vector and a motion feature vector; analyzing the audio signal for each short-term video slice to determine an audio feature vector; forming a plurality of short-term audio-visual atoms for each short-term video slice by combining the visual feature vector and the motion feature vector for a particular region track with the corresponding audio feature vector; and using a classifier to determine a classification for the video segment responsive to the short-term audio-visual atoms.

    Abstract translation: 一种用于确定视频段的分类的方法，包括以下步骤：将视频段分解成多个短视频片段，每个短片段包括多个视频帧和音频信号; 分析每个短期视频片段的视频帧以形成多个区域轨道; 分析每个区域轨迹以形成视觉特征向量和运动特征向量; 分析每个短期视频片段的音频信号以确定音频特征向量; 通过将特定区域轨道的视觉特征向量和运动特征向量与相应的音频特征向量组合，形成每个短期视频片段的多个短期视听原子; 并且使用分类器来确定响应于短期视听原子的视频片段的分类。

    NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same
    52.
    发明授权
    NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same 失效
    具有并行位线和源极线的NAND / NOR闪存单元，阵列和存储器件，具有可编程选择选通晶体管，以及用于操作相同的电路和方法

    公开(公告)号：US08120959B2

    公开(公告)日：2012-02-21

    申请号：US12455337

    申请日：2009-06-01

    Applicant: Peter Wung Lee ,  Fu-Chang Hsu

    Inventor： Peter Wung Lee ,  Fu-Chang Hsu

    IPC: G11C16/04

    CPC classification number: G11C16/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3436 ,  G11C2211/5644

    Abstract: A nonvolatile memory device includes a nonvolatile memory array including a plurality of charge retaining transistors arranged in rows and columns. The device has a plurality source lines formed in parallel with the bit lines associated with each column. Row decode/driver circuits are connected to blocks of the charge retaining transistors for controlling the application of the necessary read, program, and erase signals. Erase count registers, each of the erase count registers associated with one block of the array of the charge retaining transistors for storing an erase count for the associated block for determining whether a refresh operation is to be executed. Groupings on each column of the array of charge retaining transistors are connected as NAND series strings where each NAND string has a select gating charge retaining transistor connected to the top charge retaining transistor for connecting the NAND series string to the bit lines.

    Abstract translation: 非易失性存储器件包括非易失性存储器阵列，其包括以行和列排列的多个电荷保持晶体管。 该装置具有与与每列相关联的位线并联形成的多条源极线。 行解码/驱动器电路连接到电荷保持晶体管的块，用于控制所需的读取，编程和擦除信号的应用。 擦除计数寄存器，每个擦除计数寄存器与电荷保持晶体管阵列的一个块相关联，用于存储相关块的擦除计数，以确定是否执行刷新操作。 电荷保持晶体管阵列的每列上的分组被连接为NAND串联串行，其中每个NAND串具有连接到顶部电荷保持晶体管的选择栅极电荷保持晶体管，用于将NAND串联连接到位线。

    Novel embedded NOR flash memory process with NAND cell and true logic compatible low voltage device
    54.
    发明申请
    Novel embedded NOR flash memory process with NAND cell and true logic compatible low voltage device 失效
    新型嵌入式NOR闪存过程与NAND单元和真正逻辑兼容的低电压器件

    公开(公告)号：US20120001233A1

    公开(公告)日：2012-01-05

    申请号：US13135220

    申请日：2011-06-29

    Applicant: Peter Wung Lee ,  Han-Rei Ma ,  Fu-Chang Hsu

    Inventor： Peter Wung Lee ,  Han-Rei Ma ,  Fu-Chang Hsu

    IPC: H01L23/52 ,  H01L21/8246

    CPC classification number: H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66825 ,  H01L29/7881

    Abstract: An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.

    Abstract translation: 由非易失性存储器阵列电路，逻辑电路和线性模拟电路形成的集成电路形成在基板上。 非易失性存储器阵列电路，逻辑电路和线性模拟电路由通过浅沟槽隔离形成的隔离区隔开。 非易失性存储器阵列电路形成为三重阱结构。 非易失性存储器阵列电路是由至少两个串联连接的浮栅晶体管形成的基于NAND的NOR存储器电路，使得浮栅晶体管中的至少一个用作选择栅极晶体管，以防止漏电流通过电荷保持晶体管， 电荷保持晶体管不被选择用于读取。 基于NAND的NOR存储器电路的每列与一个位线和一个源极线相关联并连接到一个位线和一个源极线。

    MOUNTING A PELLICLE TO A FRAME
    55.
    发明申请
    MOUNTING A PELLICLE TO A FRAME 有权
    安装一个框架到一个框架

    公开(公告)号：US20110294048A1

    公开(公告)日：2011-12-01

    申请号：US13208300

    申请日：2011-08-11

    Applicant: Florence Eschbach ,  Paul Zimmerman ,  Alexander Tregub ,  Fu-Chang Lo

    Inventor： Florence Eschbach ,  Paul Zimmerman ,  Alexander Tregub ,  Fu-Chang Lo

    IPC: G03F1/00

    CPC classification number: G03F1/64 ,  Y10T428/3154 ,  Y10T428/31544

    Abstract: A pellicle membrane is mounted between an outer frame and an inner frame. At least one of the frames is attached to the reticle without using conventional adhesives. The pellicle and reticle may be used in a lithography system. The pellicle allows radiation to pass through the pellicle to the reticle and may prevent particles from passing through the pellicle.

    Abstract translation: 防护薄膜组件安装在外框架和内框架之间。 至少一个框架不使用传统的粘合剂连接到掩模版上。 防护薄膜组件和掩模版可用于光刻系统。 防护薄膜组件允许辐射通过防护薄膜到掩模版，并且可以防止颗粒通过防护薄膜。

    DRAM-LIKE NVM MEMORY ARRAY AND SENSE AMPLIFIER DESIGN FOR HIGH TEMPERATURE AND HIGH ENDURANCE OPERATION
    56.
    发明申请
    DRAM-LIKE NVM MEMORY ARRAY AND SENSE AMPLIFIER DESIGN FOR HIGH TEMPERATURE AND HIGH ENDURANCE OPERATION 失效
    类似DRAM的NVM存储器阵列和感测放大器设计用于高温和高耐压运行

    公开(公告)号：US20110267883A1

    公开(公告)日：2011-11-03

    申请号：US13094836

    申请日：2011-04-27

    Applicant: PETER WUNG LEE ,  FU-CHANG HSU

    Inventor： PETER WUNG LEE ,  FU-CHANG HSU

    IPC: G11C14/00 ,  G11C16/04

    CPC classification number: G11C16/0441 ,  G11C16/045

    Abstract: A DRAM-like non-volatile memory array includes a cell array of non-volatile cell units with a DRAM-like cross-coupled latch-type sense amplifier. Each non-volatile cell unit has two non-volatile cell devices with respective bit lines and source lines running in parallel and laid out perpendicular to the word line associated with the non-volatile cell unit. The two non-volatile cell devices are programmed with erased and programmed threshold voltages as a pair for storing a single bit of binary data. The two bit lines of each non-volatile cell unit are coupled through a Y-decoder and a latch device to the two respective inputs of the latch-type sense amplifier which provides a large sensing margin for the cell array to operate properly even with a narrowed threshold voltage gap. Each non-volatile cell device may be a 2 T FLOTOX-based EEPROM cell, a 2 T flash cell, 11 T flash cell or a 1.5 T split-gate flash cell.

    Abstract translation: DRAM类非易失性存储器阵列包括具有类DRAM的交叉耦合锁存型读出放大器的非易失性单元单元的单元阵列。 每个非易失性单元单元具有两个非易失性单元设备，其各自的位线和源极线并行运行并且垂直于与非易失性单元单元相关联的字线布置。 两个非易失性单元设备被编程为擦除和编程的阈值电压作为一对用于存储单个位的二进制数据。 每个非易失性单元单元的两个位线通过Y解码器和锁存器件耦合到锁存型读出放大器的两个相应的输入端，这提供了一个较大的感测余量，使得单元阵列即使在 变窄的阈值电压差。 每个非易失性单元设备可以是基于2T FLOTOX的EEPROM单元，2T闪存单元，11T闪存单元或1.5T分裂栅极闪存单元。

    Duty feed forward method and apparatus for modulating a duty of a PWM signal and power converting method and power converter using the same
    57.
    发明授权
    Duty feed forward method and apparatus for modulating a duty of a PWM signal and power converting method and power converter using the same 有权
    用于调制PWM信号的占空比的负载前馈方法和装置以及使用其的功率转换方法和功率转换器

    公开(公告)号：US08040122B2

    公开(公告)日：2011-10-18

    申请号：US11849629

    申请日：2007-09-04

    Applicant: Tsai-Fu Chang ,  Liang-Pin Tai

    Inventor： Tsai-Fu Chang ,  Liang-Pin Tai

    IPC: G05F1/40

    CPC classification number: H03K7/08

    Abstract: The duty of a PWM signal in a power converter is extracted to feed forward to modulate the slope of a linear oscillating ramp signal or the voltage level of an error signal, so as to modulate the duty of the PWM signal, by which the transient response of the power converter and the stability of the PWM loop both are improved.

    Abstract translation: 提取功率转换器中的PWM信号的占空比以前馈以调制线性振荡斜坡信号的斜率或误差信号的电压电平，以便调制PWM信号的占空比，由此瞬态响应 的功率转换器和PWM环路的稳定性都得到了改善。

    Dopant implantation method using multi-step implants
    58.
    发明授权
    Dopant implantation method using multi-step implants 有权
    使用多步植入物的掺杂剂植入法

    公开(公告)号：US08008158B2

    公开(公告)日：2011-08-30

    申请号：US12170656

    申请日：2008-07-10

    Applicant: Tse-En Chang ,  Chih-Fu Chang ,  Bone-Fong Wu ,  Chieh Chih Ting ,  Shao Hua Wang ,  Pu-Fang Chen ,  Yen Chuang

    Inventor： Tse-En Chang ,  Chih-Fu Chang ,  Bone-Fong Wu ,  Chieh Chih Ting ,  Shao Hua Wang ,  Pu-Fang Chen ,  Yen Chuang

    IPC: H01L21/336 ,  H01L21/8236

    CPC classification number: H01L21/26513 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less than the target dopant concentration, and without annealing the substrate after the implanting step, performing at least one second implanting step to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to the target dopant concentration.

    Abstract translation: 在具有目标掺杂剂浓度的掺杂剂分布的MOS晶体管器件中形成掺杂剂注入区域的方法包括：将第一浓度的掺杂剂注入到衬底的区域中，其中掺杂剂的第一浓度小于目标掺杂剂浓度， 并且在植入步骤之后不退火衬底，执行至少一个第二注入步骤以将至少一个第二浓度的掺杂剂注入到衬底的区域中，以使该区域中的掺杂剂浓度达到目标掺杂剂浓度。

    FLOTOX-BASED, BIT-ALTERABLE, COMBO FLASH AND EEPROM MEMORY
    60.
    发明申请
    FLOTOX-BASED, BIT-ALTERABLE, COMBO FLASH AND EEPROM MEMORY 审中-公开
    基于FLOTOX，可更换，组合闪存和EEPROM存储器

    公开(公告)号：US20110199830A1

    公开(公告)日：2011-08-18

    申请号：US13015579

    申请日：2011-01-28

    Applicant: Peter Wung Lee ,  Fu-Chang Hsu

    Inventor： Peter Wung Lee ,  Fu-Chang Hsu

    IPC: G11C16/10 ,  G11C16/16

    CPC classification number: G11C16/0433 ,  G11C11/005 ,  G11C16/10

    Abstract: A non-volatile memory array having FLOTOX-based memory cells connected by a plurality of word lines and a plurality of bit lines is disclosed. In the memory array, the FLOTOX-based memory cells in a common word line do not share a common source line. Instead, the FLOTOX-based memory cells associated with a bit line are provided with a source line laid out in parallel with the bit line to avoid punch-through leakage. The FLOTOX-based memory cells may be 2T FLOTOX-based EEPROM cells or 1T FLOTOX-based flash cells. The byte-alterable and page-alterable functions of a 2T EEPROM array and the block-alterable function of a 1T flash array are preserved. In addition, a novel bit-alterable function is added to both 2T FLOTOX-based EEPROM array and 1T FLOTOX-based flash array to reduce the unnecessary high voltage over-stress in a write operation to improve program/erasure endurance cycles.

    Abstract translation: 公开了一种具有由多个字线和多个位线连接的基于FLOTOX的存储单元的非易失性存储器阵列。 在存储器阵列中，公共字线中的基于FLOTOX的存储单元不共享公共源线。 相反，与位线相关联的基于FLOTOX的存储单元被提供有与位线并行布置的源极线以避免穿透泄漏。 基于FLOTOX的存储器单元可以是基于2T FLOTOX的EEPROM单元或基于1T FLOTOX的闪存单元。 2T EEPROM阵列的字节可变和可变换的功能以及1T闪存阵列的块可更改功能得以保留。 另外，基于2T FLOTOX的EEPROM阵列和基于1T FLOTOX的闪存阵列都增加了一个新颖的位可变功能，以减少写入操作中不必要的高压过应力，从而改善程序/擦除持续时间。

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