公开(公告)号：US08169206B2

公开(公告)日：2012-05-01

申请号：US12960714

申请日：2010-12-06

Applicant: Tsai-Fu Chang ,  Liang-Pin Tai

Inventor： Tsai-Fu Chang ,  Liang-Pin Tai

IPC: G05F1/40

CPC classification number: H03K7/08

Abstract: The duty of a PWM signal in a power converter is extracted to feed forward to modulate the slope of a linear oscillating ramp signal or the voltage level of an error signal, so as to modulate the duty of the PWM signal, by which the transient response of the power converter and the stability of the PWM loop both are improved.

Abstract translation: 提取功率转换器中的PWM信号的占空比以前馈以调制线性振荡斜坡信号的斜率或误差信号的电压电平，以便调制PWM信号的占空比，由此瞬态响应 的功率转换器和PWM环路的稳定性都得到了改善。

公开(公告)号：US07498792B2

公开(公告)日：2009-03-03

申请号：US11269798

申请日：2005-11-09

Applicant: Tsai-Fu Chang ,  Liang-Pin Tai

Inventor： Tsai-Fu Chang ,  Liang-Pin Tai

IPC: G05F1/00

CPC classification number: H02M3/156 ,  H02M3/158 ,  H02M2001/0025

Abstract: A pulse-width-modulation (PWM) control system with nonlinear ramp is disclosed. A nonlinear ramp generator generates a nonlinear ramp varied with the duty (Vout/Vin) in a waveform signal, which could be a logarithm ramp, an exponent ramp, a multi-piecewise-linear ramp, a power ramp or a combination of above. The slope of the ramp is not a constant due to the non-linear characteristic. The voltage Vramp will vary with the input voltage Vin, output voltage Vout, and duty (Vout/Vin), therefore it will reduce the influence of the input voltage Vin or output voltage Vout on the modulation gain and loop gain, even to keep the modulation gain and loop gain in constant value. As mentioned-above, the present invention improves the transient response of system, the sensitivity for variation of Vin and Vout, thus it is capable of correcting the output voltage quickly, for supplying a more steady power output.

Abstract translation: 公开了具有非线性斜坡的脉宽调制（PWM）控制系统。 非线性斜坡发生器产生随波形信号中的占空比（Vout / Vin）变化的非线性斜坡，其可以是对数斜坡，指数斜坡，多分段线性斜坡，功率斜坡或上述组合。 由于非线性特性，斜坡的斜率不是常数。 电压Vramp将随着输入电压Vin，输出电压Vout和占空比（Vout / Vin）而变化，因此它将减小输入电压Vin或输出电压Vout对调制增益和环路增益的影响，甚至保持 调制增益和环路增益恒定值。 如上所述，本发明改进了系统的瞬态响应，对Vin和Vout变化的灵敏度，因此能够快速校正输出电压，以提供更稳定的功率输出。

公开(公告)号：US08040122B2

公开(公告)日：2011-10-18

申请号：US11849629

申请日：2007-09-04

Applicant: Tsai-Fu Chang ,  Liang-Pin Tai

Inventor： Tsai-Fu Chang ,  Liang-Pin Tai

IPC: G05F1/40

CPC classification number: H03K7/08

Abstract: The duty of a PWM signal in a power converter is extracted to feed forward to modulate the slope of a linear oscillating ramp signal or the voltage level of an error signal, so as to modulate the duty of the PWM signal, by which the transient response of the power converter and the stability of the PWM loop both are improved.

Abstract translation: 提取功率转换器中的PWM信号的占空比以前馈以调制线性振荡斜坡信号的斜率或误差信号的电压电平，以便调制PWM信号的占空比，由此瞬态响应 的功率转换器和PWM环路的稳定性都得到了改善。

公开(公告)号：US20060273769A1

公开(公告)日：2006-12-07

申请号：US11269798

申请日：2005-11-09

Applicant: Tsai-Fu Chang ,  Liang-Pin Tai

Inventor： Tsai-Fu Chang ,  Liang-Pin Tai

IPC: G05F1/00

CPC classification number: H02M3/156 ,  H02M3/158 ,  H02M2001/0025

Abstract: A pulse-width-modulation (PWM) control system with nonlinear ramp is disclosed. A nonlinear ramp generator generates a nonlinear ramp varied with the duty (Vout/Vin) in a waveform signal, which could be a logarithm ramp, an exponent ramp, a multi-piecewise-linear ramp, a power ramp or a combination of above. The slope of the ramp is not a constant due to the non-linear characteristic. The voltage Vramp will vary with the input voltage Vin, output voltage Vout, and duty (Vout/Vin), therefore it will reduce the influence of the input voltage Vin or output voltage Vout on the modulation gain and loop gain, even to keep the modulation gain and loop gain in constant value. As mentioned-above, the present invention improves the transient response of system, the sensitivity for variation of Vin and Vout, thus it is capable of correcting the output voltage quickly, for supplying a more steady power output.

Abstract translation: 公开了具有非线性斜坡的脉宽调制（PWM）控制系统。 非线性斜坡发生器产生在波形信号中随占空比（V OUT）/ V SUB变化的非线性斜坡，其可以是对数斜坡，指数斜坡， 多分段线性斜坡，功率斜坡或上述组合。 由于非线性特性，斜坡的斜率不是常数。 电压V 将随着中的输入电压V SUB，输出电压V OUT输出和占空比（V SUB输出 / V ），因此它将减小输入电压V 和V OUT的变化的灵敏度，因此它能够快速校正输出电压 ，用于提供更稳定的功率输出。

公开(公告)号：US07786604B2

公开(公告)日：2010-08-31

申请号：US11797779

申请日：2007-05-08

Applicant: Liang-Pin Tai

Inventor： Liang-Pin Tai

IPC: H01L23/34

CPC classification number: H01L23/49575 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device package comprises a first semiconductor die having a first source region, a first gate region, and a first drain region attached on a first leadframe, a second semiconductor die having a second source region, a second gate region, and a second drain region attached on a second leadframe, and several pins electrically connected to the leadframes and source and gate regions. The second leadframe is electrically connected to the first source region. The pins connected to the first leadframe and second source region are on a side of the package, and the pins connected to the first gate region, second leadframe, and second gate region are on another side of the package.

Abstract translation: 半导体器件封装包括第一半导体管芯，其具有第一源区域，第一栅极区域和附接在第一引线框架上的第一漏极区域，具有第二源极区域，第二栅极区域和第二漏极区域的第二半导体管芯 区域，以及连接到引线框架和源极和栅极区域的几个引脚。 第二引线框电连接到第一源区。 连接到第一引线框架和第二源极区域的引脚位于封装的一侧，并且连接到第一栅极区域，第二引线框架和第二栅极区域的引脚在封装的另一侧上。

公开(公告)号：US07701190B2

公开(公告)日：2010-04-20

申请号：US11657003

申请日：2007-01-24

Applicant: Jiun-Chiang Chen ,  Liang-Pin Tai

Inventor： Jiun-Chiang Chen ,  Liang-Pin Tai

IPC: G05F1/00

CPC classification number: H02M3/1584

Abstract: For a DC-to-DC converter including a plurality of channels for converting an input voltage to an output voltage, a control circuit comprises a load transient detector to detect the output voltage to provide a quick response signal. In a load transient, the quick response signal triggers a quick transient response period to increase the operational frequency of the converter.

Abstract translation: 对于包括用于将输入电压转换为输出电压的多个通道的DC-DC转换器，控制电路包括检测输出电压以提供快速响应信号的负载瞬变检测器。 在负载瞬变中，快速响应信号触发快速的瞬态响应周期以增加转换器的工作频率。

公开(公告)号：US20090237062A1

公开(公告)日：2009-09-24

申请号：US12385721

申请日：2009-04-17

Applicant: Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

Inventor： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC: G05F3/24

CPC classification number: H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

公开(公告)号：US20090206922A1

公开(公告)日：2009-08-20

申请号：US12385718

申请日：2009-04-17

Applicant: Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

Inventor： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC: G05F3/02

CPC classification number: H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

公开(公告)号：US20090201078A1

公开(公告)日：2009-08-13

申请号：US12385719

申请日：2009-04-17

Applicant: Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

Inventor： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC: G05F3/02

CPC classification number: H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

公开(公告)号：US07501805B2

公开(公告)日：2009-03-10

申请号：US11487388

申请日：2006-07-17

Applicant: Isaac Y. Chen ,  An-Tung Chen ,  Liang-Pin Tai

Inventor： Isaac Y. Chen ,  An-Tung Chen ,  Liang-Pin Tai

IPC: H02M3/158

CPC classification number: H02M1/36 ,  H02M3/156 ,  H02M2001/0025 ,  Y10S323/901

Abstract: A circuit and method for soft start of a system compare a feedback signal produced from an output voltage of the system with a ramp signal to generate a comparison signal, and enables the system once the comparison signal indicating the ramp signal reaches the feedback signal, such that the output voltage becomes active from a residual voltage toward a target level.

Abstract translation: 用于软启动的系统的电路和方法将从系统的输出电压产生的反馈信号与斜坡信号进行比较，以产生比较信号，并且一旦指示斜坡信号的比较信号达到反馈信号，使能系统， 输出电压从残余电压向目标电平变为有效。