公开(公告)号：US06590813B2

公开(公告)日：2003-07-08

申请号：US10180076

申请日：2002-06-27

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C1604

CPC classification number: G11C16/3445 ,  G11C5/145 ,  G11C8/08 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3459

Abstract: A semiconductor memory has a memory cell array, a boosted voltage generator to generate a boosted voltage and a decoder to select memory cells in said memory cell array in response to an address signal. The voltage generator is activated in response to input of a first command, and kept active for a period of repeated input of a second command to control for the voltage generator, following the first command. The semiconductor memory may be provided with a regular operation mode in which the voltage generator is controlled to be in an active or inactive state by means of a first command signal in response to a predetermined signal, and a successive operation mode in which the voltage generator is kept active by a second command signal in response to another predetermined signal.

公开(公告)号：US06552936B2

公开(公告)日：2003-04-22

申请号：US10052303

申请日：2002-01-18

Applicant: Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

Inventor： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

IPC: G11C1604

CPC classification number: G11C7/1021 ,  G11C8/10

Abstract: There is disclosed a semiconductor integrated circuit device comprising a memory cell array, row decoder, sense amplifier, column gate with two or more stages connected in series, column gate driving circuit, data latch, multiplexer, and address control circuit, and the multiplexer sequentially selects data corresponding to a predetermined address from a plurality of data latched by the data latch. The address control circuit reverses a driving signal for driving at least one stage of the column gate with two or more stages connected in series and selects the columns designated by the next selected plurality of addresses, while the multiplexer sequentially selects the data corresponding to the predetermined address.

公开(公告)号：US09003105B2

公开(公告)日：2015-04-07

申请号：US13603697

申请日：2012-09-05

Applicant: Ayako Yamano ,  Teruo Takagiwa ,  Koichi Fukuda ,  Hitoshi Shiga ,  Osamu Nagao

Inventor： Ayako Yamano ,  Teruo Takagiwa ,  Koichi Fukuda ,  Hitoshi Shiga ,  Osamu Nagao

IPC: G06F12/08 ,  G06F12/02 ,  G11C16/00 ,  G11C11/56 ,  G11C16/16

CPC classification number: G06F12/0891 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C11/5635 ,  G11C16/00 ,  G11C16/16 ,  Y02D10/13

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective.

Abstract translation: 根据一个实施例，半导体存储器件包括存储器单元中的多个块，每个块用作数据的擦除单元，该块包括多个页，每个页包括多个存储单元晶体管 每个存储单元晶体管被配置为基于存储单元晶体管的阈值电压的擦除状态或第一保持状态，以及控制器搜索块中的数据，将表示有效的第一标志写入到 具有擦除状态的块的规定页面，并且将表示无效的第一标志写入具有第一保持状态的块的规定页面，以第一保留状态读出块的规定页面，并且确定 当第一个标志表示有效时，块是可写的。

公开(公告)号：US20140006906A1

公开(公告)日：2014-01-02

申请号：US13719479

申请日：2012-12-19

Applicant: Hitoshi Shiga ,  Hidetaka Tsuji

Inventor： Hitoshi Shiga ,  Hidetaka Tsuji

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1072 ,  G11C2029/0411

Abstract: A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.

Abstract translation: 存储器件包括存储数据的存储器芯片和控制存储器芯片的外部控制器。 存储器芯片包括被配置为存储两个或多个位的数据的多个存储器单元; 以及内部控制器，其执行包括下页和上页程序操作的页面数据的编程操作，并且对包括下页和上页读操作的页数据执行读操作。 外部控制器包括纠错单元，对要编程到存储单元阵列中的数据进行纠错编码，并对数据执行纠错解码。 在上层读取操作中，内部控制器将读取页数据从存储单元阵列输出到外部控制器，而不管高层编程操作是否完成。

公开(公告)号：US08189395B2

公开(公告)日：2012-05-29

申请号：US12916856

申请日：2010-11-01

Applicant: Hitoshi Shiga ,  Susumu Fujimura ,  Yoshihiko Shindo

Inventor： Hitoshi Shiga ,  Susumu Fujimura ,  Yoshihiko Shindo

IPC: G11C16/26

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5646

Abstract: A nonvolatile semiconductor memory that includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section. The data reading and programming control section includes: an adjacent memory cell data reading section; an adjacent memory cell data memory section; a reading voltage level control section; a data reading section for reading the data from a first memory cell at a plurality of reading voltages corresponding to a plurality of predetermined reading voltage verify levels controlled using the reading voltage level control section; and a data determining section for determining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section.

Abstract translation: 一种非易失性半导体存储器，包括：包括多个电可写入存储单元的存储单元阵列; 连接到所述多个存储单元的多个字线和多个位线; 和数据读取和编程控制部分。 数据读取和编程控制部分包括：相邻存储单元数据读取部分; 相邻存储单元数据存储器部分; 读取电压电平控制部; 数据读取部分，用于以对应于使用读取电压电平控制部分控制的多个预定读取电压验证电平的多个读取电压读取来自第一存储器单元的数据; 以及数据确定部分，用于基于由数据读取部分读取的数据确定在第一存储器单元中哪个数据被编程。

公开(公告)号：US20120051134A1

公开(公告)日：2012-03-01

申请号：US13217512

申请日：2011-08-25

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C16/04

CPC classification number: G11C29/025 ,  G11C16/26 ,  G11C2029/1202 ,  G11C2029/5006

Abstract: When performing a word line leak test to determine a leak state of the word lines, the control circuit applies, from the voltage control circuit to the word lines connected to the memory cell array written with test pattern data, voltages corresponding to the test pattern data. Thereafter, it switches the transfer transistors to a nonconductive state, thereby setting the word lines in a floating state. After a lapse of a certain time from switching of the transfer transistors to a nonconductive state, it activates the sense amplifier circuit to perform a read operation in the memory cell array. Then it compares a result of the read operation with an expectation value corresponding to the test pattern data.

Abstract translation: 当进行字线泄漏测试以确定字线的泄漏状态时，控制电路从电压控制电路向连接到用测试图形数据写入的存储单元阵列的字线施加与测试图案数据相对应的电压 。 此后，它将转移晶体管切换到非导通状态，从而将字线设置为浮置状态。 在从转换晶体管切换到非导通状态经过一段时间之后，它激活读出放大器电路，以在存储单元阵列中执行读取操作。 然后将读取操作的结果与对应于测试图案数据的期望值进行比较。

公开(公告)号：US07941588B2

公开(公告)日：2011-05-10

申请号：US11864074

申请日：2007-09-28

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G06F12/00

CPC classification number: G06F13/28

Abstract: A nonvolatile semiconductor device includes a first flash memory device; a second flash memory device in which data programming and/or reading is faster than in said first flash memory device; an address conversion table which correlates a logical address of a memory cell to a physical address designating said memory cell of said first and/or said second flash memory; an interface part which accepts an access request to a memory cell, an address conversion table search part which searches a physical address an access part which accesses a memory cell a counting part which counts the number of times a physical address has been accessed and generates an access count value of said physical address; a comparison part which compares whether said access count value of said physical address is more than a threshold or not; and a transmitting part which transmits data to said second flash memory device.

Abstract translation: 非易失性半导体器件包括第一闪存器件; 第二闪速存储器件，其中数据编程和/或读取比在所述第一闪存器件中快; 地址转换表，其将存储器单元的逻辑地址与指定所述第一和/或所述第二闪存的所述存储单元的物理地址相关联; 接收对存储单元的访问请求的接口部分，地址转换表搜索部，其对物理地址进行访问存储单元的访问部，对计数物理地址被访问次数进行计数的计数部， 所述物理地址的访问计数值; 比较所述物理地址的所述访问计数值是否大于阈值的比较部分; 以及将数据发送到所述第二闪存装置的发送部。

公开(公告)号：US20110044106A1

公开(公告)日：2011-02-24

申请号：US12916856

申请日：2010-11-01

Applicant: Hitoshi SHIGA ,  Susumu Fujimura ,  Yoshihiko Shindo

Inventor： Hitoshi SHIGA ,  Susumu Fujimura ,  Yoshihiko Shindo

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5646

Abstract: A nonvolatile semiconductor memory that includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section. The data reading and programming control section includes: an adjacent memory cell data reading section; an adjacent memory cell data memory section; a reading voltage level control section; a data reading section for reading the data from a first memory cell at a plurality of reading voltages corresponding to a plurality of predetermined reading voltage verify levels controlled using the reading voltage level control section; and a data determining section for determining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section.

Abstract translation: 一种非易失性半导体存储器，包括：包括多个电可写入存储单元的存储单元阵列; 连接到所述多个存储单元的多个字线和多个位线; 和数据读取和编程控制部分。 数据读取和编程控制部分包括：相邻存储单元数据读取部分; 相邻存储单元数据存储器部分; 读取电压电平控制部; 数据读取部分，用于以对应于使用读取电压电平控制部分控制的多个预定读取电压验证电平的多个读取电压读取来自第一存储器单元的数据; 以及数据确定部分，用于基于由数据读取部分读取的数据确定在第一存储器单元中哪个数据被编程。

公开(公告)号：US20110044103A1

公开(公告)日：2011-02-24

申请号：US12838811

申请日：2010-07-19

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/3436

Abstract: A nonvolatile semiconductor memory device comprises: a memory cell array configured by a plurality of first and second lines and a plurality of memory cells, each of the memory cells being selected by the first and second lines and being configured to store multiple-bit data in a nonvolatile manner; a data bus configured to transmit write data to be written to the plurality of memory cells, the write data being configured by a plurality of unit data; a column selection unit configured by a plurality of data latches, each of the data latches being configured to directly receive the unit data inputted from the data bus and to retain the unit data; and a control unit configured to control activation/non-activation of the data latches. During a programming operation, for each unit data inputted to the column selection unit, the control unit activates one of the data latches corresponding to a certain one of the memory cells where the unit data is to be stored.

Abstract translation: 非易失性半导体存储器件包括：由多个第一和第二线路以及多个存储器单元配置的存储器单元阵列，每个存储单元由第一和第二线路选择，并被配置为存储多位数据 非挥发性; 数据总线，被配置为发送要写入到所述多个存储器单元的写入数据，所述写入数据由多个单位数据配置; 由多个数据锁存器配置的列选择单元，每个数据锁存器被配置为直接接收从数据总线输入的单元数据并保持单元数据; 以及控制单元，被配置为控制数据锁存器的激活/非激活。 在编程操作期间，对于输入到列选择单元的每个单元数据，控制单元激活对应于要存储单元数据的存储单元中的某一个存储单元的数据锁存器之一。

公开(公告)号：US07800136B2

公开(公告)日：2010-09-21

申请号：US11858556

申请日：2007-09-20

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: H01L27/10

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: The height H of several kinds of basic cell are made the same and several kinds of macro cell which have a length which is an integral multiplication of the height H of this basic cell, are prepared, the basic cell and macro cell are mixed and the circuit of a peripheral circuit is designed. A M0 wire of a first wiring layer which is formed on a semiconductor substrate is used as a wire used within a macro cell. The basic cell and the macro cell are connected by a M1 wire of a second wiring layer which is formed on the first wiring layer and a M2 wire M2 of a third wiring layer. The transistor layout of basic cells and macro cells is designed and verified in advance and stored in a cell library, and auto routing by a standard method may be carried out.

Abstract translation: 使几种基本单元的高度H相同，并且准备长度为该基本单元的高度H的整数倍的几种宏单元，将基本单元和宏单元混合，并且 设计外围电路的电路。 使用形成在半导体基板上的第一布线层的M0线作为在宏电池内使用的导线。 基本单元和宏单元通过形成在第一布线层上的第二布线层的M1线和第三布线层的M2线M2连接。 基本单元和宏单元的晶体管布局预先设计和验证并存储在单元库中，并且可以执行通过标准方法的自动布线。