公开(公告)号：US20120119764A1

公开(公告)日：2012-05-17

申请号：US13181921

申请日：2011-07-13

申请人： Tae Sik YUN ,  Jong Chern LEE

发明人： Tae Sik YUN ,  Jong Chern LEE

IPC分类号： G01R31/00

CPC分类号： G01R31/31724 ,  G11C29/14 ,  G11C29/46 ,  G11C29/78 ,  G11C29/802

摘要： Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block.

摘要翻译： 公开了半导体装置的测试模式控制电路的各种实施例及相关方法。 在一个示例性实施例中，测试模式控制电路可以包括：测试模式控制块，被配置为响应于顺序地输入的第一地址信号组和第二地址信号组而产生多个控制信号集; 测试模式传送块，被配置为将根据所述多个控制信号组的组合产生的多个测试模式信号传送到所述半导体装置的多个电路块; 以及配置成将多个控制信号组发送到测试模式传送块的多个全局线。

公开(公告)号：US08143925B2

公开(公告)日：2012-03-27

申请号：US12753442

申请日：2010-04-02

申请人： Seung-Joon Ahn ,  Jong-Chern Lee

发明人： Seung-Joon Ahn ,  Jong-Chern Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0816 ,  H03L7/0814

摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

摘要翻译： 延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。 复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。 分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。 脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。 代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。 延迟线响应于代码值延迟时钟信号。

公开(公告)号：US20110204950A1

公开(公告)日：2011-08-25

申请号：US12970623

申请日：2010-12-16

申请人： Jae Bum KO ,  Jong Chern LEE ,  Sang Jin BYEON

发明人： Jae Bum KO ,  Jong Chern LEE ,  Sang Jin BYEON

IPC分类号： H03H11/26

CPC分类号： H03K5/1506 ,  H03K5/05

摘要： A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.

摘要翻译： 延迟电路包括：延迟单元，被配置为接收时钟信号，按预定时间间隔顺序地延迟输入信号，并输出多个第一延迟信号; 以及选择单元，被配置为基于一个或多个选择信号来选择所述多个第一延迟信号中的一个，并输出第二延迟信号。

公开(公告)号：US20110187444A1

公开(公告)日：2011-08-04

申请号：US12839287

申请日：2010-07-19

申请人： Sin Hyun JIN ,  Jong Chern Lee

发明人： Sin Hyun JIN ,  Jong Chern Lee

IPC分类号： G05F3/02

CPC分类号： G05F3/02

摘要： A voltage trimming circuit of a semiconductor memory apparatus may include a first voltage generation block configured to select voltage levels of a first node and a second node and divide a voltage between the first node and the second node to generate a first division voltage group; a second voltage generation block configured to select voltage levels of a third node and a fourth node and divide a voltage between the third node and the fourth node to generate a second division voltage group; a first switch block configured to select one division voltage of the first division voltage group to output the selected division voltage as a first reference voltage; and a second switch block configured to select one division voltage of the second division voltage group to output the selected division voltage as a second reference voltage.

摘要翻译： 半导体存储装置的电压调整电路可以包括第一电压产生块，其被配置为选择第一节点和第二节点的电压电平，并且在第一节点和第二节点之间划分电压以产生第一分割电压组; 第二电压产生块，被配置为选择第三节点和第四节点的电压电平，并且在第三节点和第四节点之间划分电压以产生第二分压电压组; 第一开关块，被配置为选择所述第一分压电压组的一个分压，以输出所选择的分压，作为第一参考电压; 以及第二开关块，被配置为选择所述第二分压电压组的一个分压，以将所选择的分压作为第二参考电压输出。

公开(公告)号：US20100315896A1

公开(公告)日：2010-12-16

申请号：US12650073

申请日：2009-12-30

申请人： JE-YOON KIM ,  Jong Chern Lee

发明人： JE-YOON KIM ,  Jong Chern Lee

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626

摘要： A temperature detection circuit of a semiconductor memory apparatus includes a fixed period oscillator, a temperature variable signal generating unit and a counting unit. The oscillator is configured to generate a fixed period oscillator signal when an enable signal is enabled. The temperature variable signal generating unit is configured to generate a temperature variable signal whose enable interval varies based on temperature variations, when the enable signal is enabled. The counting unit is configured to count the oscillator signal during the enable interval of the temperature variable signal to generate a temperature information signal.

摘要翻译： 半导体存储装置的温度检测电路包括固定周期振荡器，温度可变信号发生单元和计数单元。 振荡器被配置为当启用使能信号时产生固定周期振荡器信号。 温度可变信号发生单元被配置为当使能信号被使能时，产生其使能间隔基于温度变化而变化的温度可变信号。 计数单元被配置为在温度可变信号的使能间隔期间对振荡器信号进行计数，以产生温度信息信号。

公开(公告)号：US07847620B2

公开(公告)日：2010-12-07

申请号：US12136429

申请日：2008-06-10

申请人： Jong Sam Kim ,  Jong Chern Lee

发明人： Jong Sam Kim ,  Jong Chern Lee

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/073 ,  G11C5/145 ,  H02M1/32 ,  H02M2001/008

摘要： A charge pumping circuit consumes less current by reducing the number of charge pumps operating simultaneously. The charge pumping circuit includes a voltage sensor that detects a level of a high voltage and outputs a control signal based on the detection result. An oscillator provides an oscillating clock signal in response to the control signal of the voltage sensor, and the oscillator sequentially outputs the clock signal as a plurality of clock signals having shifted phases A plurality of high-voltage pumps are disposed in a plurality of regions to pump the high voltage in response to the clock signals and a different phase is designated for each region.

摘要翻译： 电荷泵浦电路通过减少同时工作的电荷泵的数量来消耗较少的电流。 电荷泵送电路包括检测高电平的电压传感器，并且基于检测结果输出控制信号。 振荡器响应于电压传感器的控制信号提供振荡时钟信号，并且振荡器顺序地输出时钟信号作为多个具有偏移相位的时钟信号，多个高压泵被设置在多个区域中 根据时钟信号泵送高电压，并为每个区域指定不同的相位。

公开(公告)号：US07705636B2

公开(公告)日：2010-04-27

申请号：US11964243

申请日：2007-12-26

申请人： Je Yoon Kim ,  Jong Chern Lee

发明人： Je Yoon Kim ,  Jong Chern Lee

IPC分类号： H03B1/00

CPC分类号： H03K5/2481 ,  H03K19/018578

摘要： The present invention relates to a buffer circuit of a semiconductor memory device, and includes a common bias supply unit and a plurality of interface units having a differential amplifying structure. Each interface unit receives an input signal and differentially amplifies the input signal and a common bias. The common bias supply unit is driven by a reference voltage to provide the common bias signal to each of the interface units. The buffer circuit makes it possible to reduce the area occupied by the buffer circuit in a semiconductor memory device.

摘要翻译： 本发明涉及一种半导体存储器件的缓冲电路，包括一个公共偏置电源单元和多个具有差分放大结构的接口单元。 每个接口单元接收输入信号并差分地放大输入信号和公共偏压。 公共偏置电源单元由参考电压驱动，以向每个接口单元提供公共偏置信号。 缓冲电路使得可以减小半导体存储器件中的缓冲电路占用的面积。

公开(公告)号：US07622962B2

公开(公告)日：2009-11-24

申请号：US11826924

申请日：2007-07-19

申请人： Dae-Suk Kim ,  Jong Chern Lee

发明人： Dae-Suk Kim ,  Jong Chern Lee

IPC分类号： G01R19/00

CPC分类号： G11C7/08

摘要： A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided. The sense amplifier control signal generating circuit includes a timing control unit that models a transmission path of data from a memory cell to a sense amplifier through a bit line and generates a timing control signal at a sensing timing when the sense amplifier starts a sensing operation. A sense amplifier control signal generating unit receives the timing control signal and generates a sense amplifier control signal.

摘要翻译： 提供一种半导体存储装置的读出放大器控制信号发生电路。 读出放大器控制信号产生电路包括定时控制单元，其通过位线对来自存储单元的数据的传输路径进行建模，并在读出放大器开始感测操作时在感测定时产生定时控制信号。 读出放大器控制信号发生单元接收定时控制信号并产生读出放大器控制信号。

公开(公告)号：US20090066371A1

公开(公告)日：2009-03-12

申请号：US11964243

申请日：2007-12-26

申请人： Je Yoon KIM ,  Jong Chern LEE

发明人： Je Yoon KIM ,  Jong Chern LEE

IPC分类号： H03K3/00

CPC分类号： H03K5/2481 ,  H03K19/018578

摘要： The present invention relates to a buffer circuit of a semiconductor memory device, and includes a common bias supply unit and a plurality of interface units having a differential amplifying structure. Each interface unit receives an input signal and differentially amplifies the input signal and a common bias. The common bias supply unit is driven by a reference voltage to provide the common bias signal to each of the interface units. The buffer circuit makes it possible to reduce the area occupied by the buffer circuit in a semiconductor memory device.

摘要翻译： 本发明涉及一种半导体存储器件的缓冲电路，包括一个公共偏置电源单元和多个具有差分放大结构的接口单元。 每个接口单元接收输入信号并差分地放大输入信号和公共偏压。 公共偏置电源单元由参考电压驱动，以向每个接口单元提供公共偏置信号。 缓冲电路使得可以减小半导体存储器件中的缓冲电路占用的面积。

公开(公告)号：US06998901B2

公开(公告)日：2006-02-14

申请号：US10880039

申请日：2004-06-29

申请人： Jong Chern Lee

发明人： Jong Chern Lee

IPC分类号： G11C7/00

CPC分类号： H03K3/0231 ,  G11C5/147 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4065

摘要： Provided is a self refresh oscillator which includes a plurality of inverters serially connected between an input terminal and an output terminal; a pull up driver for charging a first node in accordance with a level of the output terminal; a comparator for comparing a potential of the first node with a reference voltage and outputting the result to the input terminal; and a period adjusting unit for operating based on a level of the output terminal and adjusting an amount of current discharged into a ground of the first node in accordance with a temperature.

摘要翻译： 提供一种自刷新振荡器，其包括串联连接在输入端子和输出端子之间的多个反相器; 上拉驱动器，用于根据输出端的电平对第一节点充电; 比较器，用于将第一节点的电位与参考电压进行比较，并将结果输出到输入端; 以及周期调整单元，用于根据输出端子的电平进行操作，并且根据温度调节放电到第一节点的接地中的电流量。